Abstract: A packaged electronic device includes connection contacts that are formed on the contact pads on the second surface of the substrate. In contrast to the prior art, the connection contacts are not solder contacts but are formed of nickel/aluminum plated copper and are therefore harder and less malleable and subject to deformation than prior art solder balls. The connection contacts are formed to align with, and contact, attachment pads formed on the motherboard or other system component. A tension device is then used to mechanically attach the packaged electronic device of the invention to the motherboard.

Abstract: A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic primary storage elements. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.

Abstract: A lossless compression mechanism for compressing and restoring data elements such as text, text formatting, video, audio, speech, and 2D and 3D graphical information. Each data element is compressed using a data structure having a bin number field and an offset field. The bin number field is associated to a bin having a range of values which includes the data element value. The offset field is computed from a minimum bin value, wherein the minimum bin value is associated to the bin and is stored in a bin lookup table. The bin number field is encoded using a unary code, and the offset is encoded using a binary code.

Abstract: A tool for computing noise coupled onto victim lines from aggressor lines of an integrated circuit has code for traversing a victim line of the integrated circuit layout to measure its length, its average width, a coupling length, and a harmonic mean of spacing between the victim line and aggressor lines. The tool has code for computing a resistance, estimated coupling capacitance, and total capacitance of the victim line from these parameters.

Abstract: A electro-desorption compression system according to the present invention comprises an enclosure which includes first and second spaced-apart electrical conductors, a sorbent which is positioned in the enclosure between the first and second conductors, a sorbate which is capable of combining with the sorbent in an adsorption reaction to form a sorbate/sorbent compound, a power supply which is connected to the first and second conductors and which generates an electrical current that is conducted through the sorbate/sorbent compound to desorb the sorbate from the sorbent in a desorption reaction, a controller which selectively activates the power supply to initiate and terminate each desorption reaction, and a transducer which is connected to the controller and which generates a signal indicative of the end of each desorption reaction.

Abstract: A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic primary storage elements. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.

Abstract: A structure includes holes formed in a layer of tape. The holes are aligned over active areas on chips formed in a wafer. A custom vacuum chuck with a plurality of suction ports is aligned on the tape such that the suction ports contact only the tape and not the hole portions. Flats of the custom vacuum chuck are formed so that a perimeter of the flats contacts, and rests on, the tape. In addition, the flats of the custom vacuum chuck are formed so that the flats cover the entire active area on the first surface of each of the chips. Consequently, the combination of the custom vacuum chuck and the single layer of tape form a protective cavity over the active areas of the chips during singulation from the wafer.

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

Abstract: A structure including volatile memory devices that are used by the host computer system as the storage media. The volatile memory devices include volatile memory device back up systems to provide power to both the volatile memory and non-volatile memory in the event of power failure. The volatile memory devices also connect directly to an expansion bus of the host computer system, such as a PCI bus. Therefore, the volatile memory devices of the invention include a high-speed path to the host computer system and the volatile memory devices of the invention are faster than prior art devices, use less power and are lower cost.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A field and/or customer replaceable packaged refrigeration heat sink module is suitable for use in standard electronic component environments. The field replaceable packaged refrigeration heat sink module is self-contained and is specifically designed to have physical dimensions similar to those of a standard air-based cooling system, such as a fined heat sink or heat pipe. As a result, the field replaceable packaged refrigeration heat sink module can be utilized in existing electronic systems without the need for board or cabinet/rack modification or the “plumbing” associated with prior art liquid-based cooling systems.

Abstract: Clocked charge recycling differential logic circuits are activated by a delayed clock. According to the invention, when clocked charge recycling differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked charge recycling differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked charge recycling differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked charge recycling differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked charge recycling differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A method and structure for supply gating low power electronic components uses low threshold gating transistors. The low power components operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors, the leakage current of the devices, and therefore the standby power dissipation, can be minimized by using any one, or a combination of, four methods including: overdriving the low threshold gating transistors on; overdriving the low threshold gating transistors off; combining very low threshold device transistors with low threshold gating transistors; and providing the low threshold gating transistors with back bias.

Abstract: Modified full-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.

Abstract: Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and the low threshold transistors have the same channel dimensions, i.e., the same channel length and width. In order to meet this requirement and still provide a feedback signal of sufficient strength, latches according to the invention include feedback stages with multiple inverters. By using only transistors of the same channel length and width in the latches of the invention, the voltage scalability of the latches of the invention is increased significantly over that of prior art latches.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: Modified full-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.

Abstract: Low voltage latches are designed such that the latch components are comprised of low threshold transistors. To overcome the effects of leakage current and ensure proper latch operation, according to the invention, the channel widths of the low threshold transistors making up the feedback components of the latch are larger than the channel widths of the low threshold transistors making up the storage components of the latch. Using the method and structure of the invention, the voltage scalability of the latch is significantly increased. One embodiment of the invention allows for minimum supply voltages of around 120 millivolts, an improvement of over six hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

Abstract: A method and apparatus for testing processes in a computer system are described. In a software process, there exist many test points in the execution of the process where stress testing may be applied. The process is executed with stress testing applied at selected test points and test intervals. The selected test points are based on prime numbers and varied for successive execution iterations. An efficient distribution of evaluated test points is achieved, and all possible test points are ultimately evaluated within a small number of execution iterations. In one embodiment, the total number of test points is first determined. A first execution run is evaluated at selected test points that correspond to prime numbers greater than the square root of the total number of test points.

Abstract: An electronic device, such as a sensor die, is packaged by first forming a hole through a substrate. The hole is made large enough to position the entire electronic device within the hole. A tape is then applied to the second surface of the substrate to cover a second side of the hole, thereby creating a tape surface at the bottom of the hole. The electronic device is then positioned within the hole such that the electronic device is in contact with, and adhered to, the tape surface at the bottom of the hole. Electronic connections are made between the electronic device and the substrate and a layer of encapsulant is applied. In one embodiment, the electronic device is a sensor die and an optical element is positioned over an active region of the sensor die before the encapsulant is applied. The encapsulant then surrounds and holds the optical element in position over the active region of the sensor die.