Abstract: A technique for indexing data is provided. A method for compressing an index to obtain a compressed index that is easily stored and transmitted is provided. The invention also provides for the decompression of such a compressed index. One embodiment of the invention maintains a separate index for each document, thereby allowing easy updating of indexes in response to changes in documents and easy transmission of indexes, which allows distributed searching. The technique provides very compact indexing information, but allows the indexing information to be very rapidly processed.

Abstract: An automated method of analyzing crosstalk in a digital logic integrated circuit on a digital computer is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. The netlist has gate and black box invocations as well as transistor invocations. Library models are used to find driving resistances and capacitances associated with the gate and black-box invocations. For at least one potential victim wire of the plurality of wires, a subset of the wires of the chip are found to be potential aggressor wires to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire.

Abstract: A method and apparatus for performing power routing in ASIC design. Power routing is performed after cell placement, allowing more knowledgeable placement of power structures in the physical layout. By performing cell placement prior to power routing, standard cells are allowed to be placed in more optimal configurations. In one embodiment, power rings and power straps are placed over the top of the standard cells based on power analysis of the standard cell layout. Those regions of the layout where design violations are triggered are corrected by an incremental placement correction of affected cells. In another embodiment, cells are placed in the physical layout in a bottom-up hierarchical manner. When a given cell becomes large enough to require power routing, a power feed cell of sufficient dimension to support the necessary power strap is inserted into the layout during the placement process. In the subsequent power routing phase, power straps are placed over the power feed cells.

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

Abstract: A computing environment that offers a level of decentralization wherein application server code resident on a remote application server can be distributed to a local server. The local server becomes a local application server for a client. A request for information by a client is serviced by the local application server. If the information is available on the local application server, the local application server satisfies the request using this information. If the information is not available locally, the local application server can access the remote application server to obtain the requested information. When the information is copied to the local application server, the local application server retains a copy of the information and forwards a copy to the client. Thus, subsequent requests can be satisfied without accessing the remote application server.

Abstract: A method for forming a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components is disclosed. The snapable multi-package substrate is formed with trenches that separate and define sections where individual packaged electronic components are fabricated in a snapable multi-package array, and where individual packaged electronic components are singulated from the snapable multi-package array of the invention by simply applying hand pressure to break or “snap” individual packaged electronic components apart.

Abstract: A high density, high speed, and low power circuit scheme is presented for vector switching port applications for advanced IC design. Embodiments exhibit superior area-delay-power properties. The technique benefits a wide range of product applications ranging from high speed high bandwidth router to low power portable computing hardware. 5.0 TBPS peak traffic can be supported for an on-chip vector port.

Abstract: A plurality of pressure sensor dice are attached to an array of pressure sensor die attach sites located on a substrate. The pressure sensor dice are then electrically connected to the pressure sensor die attach sites using standard wire bond techniques. The resulting array of pressure sensor sub-assemblies is then molded, using a mold tool that closes on three sides of the substrate so that a cavity is formed that is open on the fourth side. A portion of the outer surface of the micro-machine element of each pressure sensor die is left exposed at the bottom of a cavity or hole in the encapsulant. After molding, the exposed outer surface of the micro-machine element is covered with a pressure coupling gel applied in the cavity. The resulting array of packaged pressure sensors are then sigulated using well know sawing or laser techniques or by snapping a specially formed snap array.

Abstract: The invention is a method and apparatus for clipping a function, such as a quadratic Bezier function defining a shading characteristic of an object being modeled. In accordance with the invention, a second or higher order function is clipped in “linear” fashion using barycentric coordinates. In accordance an embodiment of the invention, the method comprises the steps of determining a second or higher order function to be clipped, determining barycentric coordinates for at least one clipping point associated with a first order (i.e. linear) function associated with the second or higher order function and generating at least one clipping point associated with the second or higher order function using the barycentric coordinates. In one or more embodiments of the invention, the method includes the steps of using the barycentric coordinates to determine a reparameterized clipped function.

Abstract: A plurality of pressure sensor dice are attached to an array of pressure sensor die attach sites located on a custom substrate having holes. The pressure sensor dice are then electrically connected to the pressure sensor die attach sites using standard flip chip techniques. The resulting array of pressure sensor sub-assemblies is then molded, so that a cavity is formed that is open at the bottom of each hole in the custom substrate. A portion of the outer surface of the micro-machine element of each pressure sensor die is left exposed at the bottom of the hole in the substrate. After molding, the exposed outer surface of the micro-machine element is covered with a pressure coupling gel applied in the hole. The resulting array of packaged pressure sensors are then sigulated using well know sawing or laser techniques or by snapping a specially formed snap array.

Abstract: A multi-level cache and method for operation therefore includes a first non-blocking cache receiving access requests from a device in a processor, and a first miss queue storing entries corresponding to access requests not serviced by the first non-blocking cache. A second non-blocking cache is provided for receiving access requests from the first miss queue, and a second miss queue is provided for storing entries corresponding to access requests not serviced by the second non-blocking cache. Other queueing structures such as a victim queue and a write queue are provided depending on the particular structure of the cache level within the multilevel cache hierarchy.

Abstract: A structure comprises a substrate with electronic components formed on a first surface of the substrate. The structure includes a scribe line on a first surface of the substrate. The structure includes a trench formed by a laser on the second or back-side surface of the substrate, thus protecting the front-side surface of the substrate and, more particularly, the electronic component such as an integrated circuit and/or functional unit on the front-side surface of the substrate during singulation. Since, according to the invention, no saw blade is used, the width of the scribe line does not need to be any larger than the width of the beam from the laser plus some minimal tolerance for alignment. As a result, using the invention, the width of scribe line is on the order of twenty-four times smaller than the width of scribe lines required by the prior art methods.

Abstract: The invention is a method and apparatus for chording. One embodiment of an apparatus comprises a user-wearable support element, in the form of a glove having finger and thumb portions. An output generating element in the form of a switch is provided corresponding to each finger and thumb portion of the glove. An activator is provided for each finger and thumb portion of the glove. In one embodiment, each activator comprises a wire having one end connected to the glove and a second end arranged to activate the switch corresponding to its respective finger or thumb portion. Movement of each finger and thumb into one or more positions causes the respective activator to activate its respective switch. In one embodiment, the outputs generated by the switches are input to a signal controller. The signal controller is arranged to provide a second output dependent upon the inputs from the various switches. In one embodiment, the second output is determined from a map and comprises alphanumeric data.

Abstract: A plurality of pressure sensor dice are attached to an array of pressure sensor die attach sites located on a substrate. The pressure sensor dice are then electrically connected to the pressure sensor die attach sites using standard wire bond techniques. The resulting array of pressure sensor sub-assemblies is then molded, using a mold tool which closes on three sides of the substrate so that a cavity is formed that is open on the fourth side. A portion of the outer surface of the micro-machine element of each pressure sensor die is left exposed at the bottom of a cavity or hole in the encapsulant. After molding, the exposed outer surface of the micro-machine element is covered with a pressure coupling gel applied in the cavity. The resulting array of packaged pressure sensors are then sigulated using well know sawing or laser techniques or by snapping a specially formed snap array.

Abstract: A wafer is singulated from the back-side surface of the wafer using laser ablation, thus protecting the front-side surface of the wafer and, more particularly, the integrated circuits and/or functional units on the front-side surface. Since, according to the invention, no saw blade is used, the width of the scribe lines does not need to be any larger than the width of the beam from the laser plus some minimal tolerance for alignment. As a result, using the invention, the width of scribe lines is on the order of twenty-four times smaller than the width of scribe lines required by the prior art methods.

Abstract: An electronic device, such as a sensor die, is packaged by first forming a hole through a substrate. The hole is made large enough to position the entire electronic device within the hole. A tape is then applied to the second surface of the substrate to cover a second side of the hole, thereby creating a tape surface at the bottom of the hole. The electronic device is then positioned within the hole such that the electronic device is in contact with, and adhered to, the tape surface at the bottom of the hole. Electronic connections are made between the electronic device and the substrate and a layer of encapsulant is applied. In one embodiment, the electronic device is a sensor die and an optical element is positioned over an active region of the sensor die before the encapsulant is applied. The encapsulant then surrounds and holds the optical element in position over the active region of the sensor die.

Abstract: In accordance with the present invention, a cache memory subsystem includes a processor, a cache control unit and a SRAM serving as the cache memory. The SRAM is a synchronous SRAM. The cache control unit provides appropriately timed control signals to the SRAM when the processor is accessing the cache memory. The SRAM can be either a pipelined architecture SRAM (register output SRAM) or a flow-through access architecture SRAM (latch output SRAM). The cache control unit is selectably configured to operate in a pipelined mode (1-1-1) or a flow-through (2-2) mode. The cache control unit is configured in the 1-1-1 mode when the SRAM is a pipelined architecture SRAM having a clock rate equal to the processor. When the SRAM is a flow-through architecture SRAM that cannot be clocked at the same rate as the processor, the cache control unit is configured in the 2-2 mode and the SRAM is clocked at a clock rate half of the processor clock rate.

Abstract: A transistor is added to prior art domino logic circuits to create a modified domino logic circuit with a resistor divider connected between a first internal node and a second internal node. The resistor divider keeps the second internal node at a voltage that is higher than a second supply voltage VSS at the beginning of the evaluation phase of modified domino logic circuit. Consequently, the first internal node of the modified domino logic circuit will not start discharging until a higher voltage is reached by input signals. Thus, the input noise rejection of the modified domino logic circuits of the present invention is improved compared with prior art domino logic circuits.

Abstract: To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

Abstract: An instruction fetch unit for fetching instructions from an instruction cache of a processor. The fetch unit includes a next fetch address mechanism generating predicted next fetch addresses, the next fetch address mechanism generating a next fetch address for a fetch bundle over at least two cycles of the processor. The next fetch address mechanism determines the next fetch address based on whether a control transfer instruction from an intermediate set of fetched instructions is taken.