Abstract: In a data processing system, groups of characters to be manipulated in a predetermined manner are transferred between storage units and a central processing unit by apparatus and a method which identifies and corrects a character of a group with sign information superimposed on an identified character position for data entering the central processing unit. After identification of the character position containing the sign information superimposed on a character position, the value of the character in the identified character position is determined by apparatus removing the superimposed sign information and such value is placed in such identified character position in the entering character group. A data string including an identified character position can then be entered in the execution unit of the central processing unit for execution of instructions.

Abstract: There is disclosed herein an apparatus for automatic monitoring of numerous high speed drill spindles on a numerically controlled drilling machine for purposes of immediate detection of the absence of drilling by a particular spindle because of a broken drill bit. The apparatus detects the absence of drilling, interrupts the automatic cycle of the drilling machine and alerts the operator. Power dissipation in each drill spindle motor is compared just prior to entry of the drill bit into the workpiece and after entry if any. If power dissipation increases above a predetermined threshhold level for all spindles, no interrupt is generated. If power dissipation does not increase in one or more spindle motors, comparator circuits alert a digital processor which interrupts automatic operation of the drilling machine and alerts the operator. Such a system eliminates the expense and error of human visual monitoring and generation of expensive scrap improperly processed before discovery of the broken bit.

Abstract: In a data processing system wherein memory space in a memory unit is divided into addressable locations capable of storing a group of signals of predetermined number called signal words, and wherein an entire word or groups of entire words are exchanged between the memory unit and a central processing unit, more efficient operation of the data processing unit can be obtained if groups of related signals called operands can be stored consecutively in the addressable locations without regard to the word boundaries. Thus, operand boundaries can have arbitrary positions in boundary words. When a word containing an operand boundary is transferred to the central processing unit, non-operand data is also transferred with the word. The non-operand data occurring in the boundary words is removed from the operand signal group and stored in the central processing unit.

Abstract: In a stack for use in a data processing system memory controller, information which includes data, instructions and/or commands generated by a requesting unit requesting access to memory are accepted and temporarily stored in the stack if such memory is unavailable. The newest information from any requesting unit that must be temporarily stored is stored in the lowest unoccupied level of the stack. Associated with each stack level is a busy flip-flop which is set when the information is stored in its associated stack level. The busy flip-flop is reset when the information is given access to the memory. The level busy flip-flops are monitored to detect when the stack is full thus indicating that further requests be inhibited. By monitoring the number of levels in the stack that are filled at various times, a measure of throughput can be achieved in order to determine whether the stack should be enlarged or made smaller.

Abstract: An automation system for cutting segments from a strip of film wound on a reel, mounting the segments in reusable fixtures and stacking the fixtures in a magazine.

Abstract: This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system.The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the data group in the error correcting apparatus, the operation in progress is aborted if an error has been detected, and the error is not correctable. If correctable, the correct instruction data group is applied to the execution unit. If no error is detected in the data group, utilization of the data group proceeds uninterrupted.Two, three state busses are employed. The first three state bus is used to transmit memory data to the error detection and correction (EDAC) circuitry, to transmit corrected data from the (EDAC) circuitry and to the data output circuits and to transmit input data to the memory.

Abstract: This relates to a digital data recovery system for decoding group coded data bits stored on magnetic tape whereon a "1" is represented by a flux reversal and an "0" is represented by the absence of a flux reversal with no more than two successive zeros throughout the data record. Input logic detects transitions of input data and forwards this information to an envelope detector which determines if subsequent transitions represent valid data. The presence of valid data enables a data rate detector which determines the average data rate. An output sequencer determines when a decoded output data bit should be generated and its proper polarity.

Abstract: An improved air distribution system for cooling electronic components mounted on printed circuit boards. The system includes an air plenum chamber of rectangular cross section. Openings are formed in the side walls of the chamber to permit air under pressure from within the chamber to flow outwardly in a direction substantially normal to the outer surfaces of the side walls and over the components to be cooled. A baffle in the form of a thin sheet of metal is mounted in the plenum substantially parallel to the side walls to divide the interior into two substantially equal portions. A large number of small round holes are formed through the baffle the area of the holes occupying substantially 36 percent of the total area of the baffle. An air pump supplies air under pressure to the interior of the plenum chamber.

Abstract: This relates to an apparatus for converting raw data into GCR data and for controlling the recording of GCR data on magnetic tape. An ordered series of instructions is stored in a first programmable read only memory (PROM). A second PROM contains a special character table and a code conversion table, and receives raw data. A third PROM stores addresses which are used to access the second PROM and are indicative of whether raw data is to be converted or a special character is to be generated.

Abstract: A coding system for applying identifying data bits to a segment of a film strip having an integrated circuit bonded to a lead pattern formed on the segment by selectively piercing marking areas of the segment. A die of a punch press has a predetermined number, normally a power of 2, of pin holes which are arranged in a predetermined array. Piercing punches, one for each pin hole, are mounted on a punch holder for limited vertical movement with respect to the punch holder. The punches are arranged so each can be inserted into its corresponding pin hole. To prevent movement of piercing punches relative to the punch holder on which it is movably mounted and to vary the data applied to a segment, a backup pin is placed between a punch backup plate and the head of the piercing punch.

Abstract: A facade for enclosing data processing apparatus or similar equipment. The facade is designed to be a free-standing unit, enclosing completely a multiple-component data processing assemblage. However, the facade can also be utilized in conjunction with external structural members, such as existing walls, to enclose the assemblage. The facade is easily assembled and disassembled by available field personnel, but has sufficient structural integrity to provide protection for the enclosed equipment assemblage and to prevent casual entry into the interior. In addition, the facade has sufficient apertures to permit disapation of heat generated by the high circuit element density utilized in the modern data processing apparatus. The facade is arranged to permit easy access by the maintenance personnel to the interior of the facade.

Abstract: A programmable communications controller having a microcomputer system for buffering and controlling data communications between a communication processor and a plurality of input/output (I/O) ports of the microcomputer system to which ports/terminals can be connected directly, or indirectly, by digital data communication lines. The random access memory of the microcomputer system is divided into blocks of addresses of locations in which digital data can be stored. One of these blocks is designated as a service block. The service block in turn is divided into sectors, one for each I/O port to which is connected a communication line, for example. Each sector in the service block is adapted to have written into it and read from it data unique to the servicing of a given communication I/O port and the communication line or data terminals connected to that port. The microcomputer system of the controller is provided with an automatic addresser which is under the control of the microcomputer system.

Abstract: Method and apparatus for cleaning the top surfaces of raised input/output (I/O) terminals of semiconductor elements of a semiconductor wafer prior to electronic leads being reflow bonded to such terminals. The top surfaces of the I/O terminals substantially lie in I/O plane. The wafer is mounted on a work handler and the handler is fixedly mounted on a vacuum plate holder which is mounted for oscillatory movement in a plane at a predetermined amplitude and frequency. A vinyl eraser having a planar surface of greater area than the area of the wafer occupied by the elements is mounted directly above the wafer. The eraser is operatively connected to an actuator which presses the planar surface of the eraser against the top surfaces of the I/O terminals with a predetermined force.

Abstract: In an information handling system in which a cyclic code is utilized to both detect and correct errors and a cyclical redundancy code is used for supplementary detection of errors, the cyclical redundancy code (CRC) polynomial is chosen to be a factor of the generator polynomial, g(x), of the error detection and correction (EDAC) code. In this way, the same check bits in the code word used for error detection and correction may be further utilized for a CRC check to supplement the error detection capabilities of the system. The risk of miscorrection of data is reduced to de minimus levels by the partitioning of data and count fields in the course of the development of the error detection and correction codes. Practice of the teachings herein disclosed provides a more efficient error detection and correction system with greatly reduced risk of miscorrection. An embodiment of the invention is disclosed following the methodology taught herein.

Abstract: A fixture for use in soldering a large number of integrated circuit (IC) chips to a multilayer substrate in a single reflow soldering operation. A multilayer substrate with IC chips and their leads properly positioned on the substrate is placed within the base of the fixture. The force structure portion of the fixture is positioned on the base so that force pins, which are movable with respect to the force structure, can be lowered, or moved toward the substrate to apply the weight of a force pin to each IC chip to be soldered to the substrate. The weight, or force, of a force pin forces the back metal layer of each IC chip and its leads against a chip pad and chip lead pads of the substrate. The substrate is heated to melt, or to reflow, the solder on all the chip pads and chip lead pads. After the leads and back metal layer of each chip are wetted by the solder and while the solder is molten, the force structure is moved away from the base to remove the weight of the force pins from the IC chips.

Abstract: An electronic computer includes a plurality of printed circuit boards that are slideably mounted in spaced parallel planes within a housing. The housing contains an input/output bus arrangement which is substantially open in the middle. A power supply is detachably mounted to the housing in such a manner as to automatically connect to the input/output bus arrangement when it is secured in place. The power supply includes suction fans which draw ambient air in through the front of the housing over the printed circuit boards, through the open portion of the bus arrangement and hence over critical portions of the power supply. The air is initially drawn through perforated openings in a hinged control panel in one preferred embodiment. In another preferred embodiment, the air is drawn through a stationary member at the front of the housing.

Abstract: A logic level translator uses a current switch, a current source and a plurality of cathode followers to convert T.sup.2 L and DTL level binary signals into CML and ECL level binary signals. The translator provides isolation between the T.sup.2 L ground and the CML ground so that noise in the CML signals is reduced.

Abstract: An improved apparatus for cutting a moving web of paper comprising a cutting blade mounted on a rotary shaft at an angle to the axis of the shaft and a stationary cutting bar cooperating with the cutting blade to cut the web into paper of predetermined lengths. The apparatus is particularly suitable for cutting paper into predetermined lengths at high speeds as it is discharged from the printing system of a high-speed computer.

Abstract: A comparator circuit compares the relative magnitudes of two binary numbers. Each of the binary numbers is fed in parallel through a plurality of two-bit comparator modules corresponding to the number of two-bit pairs in the largest binary number. The binary numbers are compared order by order and simultaneously to determine one or more of five relationships between the numbers. For binary numbers greater than two bits in length, the two-bit comparator module is utilized as the basic building block and an additional level of logic circuitry is required in order to obtain an output identifying one of the relationships. Since the two-bit modules may be used interchangeably and since the relative magnitude of any two-bit grouping is generated simultaneously, the comparator circuit provides for a fast and efficient identification of relationships between two binary numbers.

Abstract: Apparatus for utilizing a logical, record oriented move instruction is disclosed. By utilizing separately maintained data field descriptors which define the attributes of the data, the move instruction is able to transfer a multitude of different data types. From a source operand the logical instruction transfers data field by field to the destination. At the time of transfer, the logical move instruction reformats the data to meet the destination's description. The move instruction is applicable both to removing data from a data file and to restoring data into the data file.