Abstract: In a data processing system having independently operating asynchronous processors, apparatus is disclosed which provides for interprocessor synchronization and/or information exchange. Synchronization interlocks and controls are provided for both identifying shared resources of a control processor and an input/output controller (IOC) processor and for obtaining control over these shared resources. If a conflict situation for any one of the shared resources arises, apparatus is disclosed whereby the IOC processor is provided the capability of assuming control over the shared resource even though the central processor has control over it. One of the shared resources is an interprocessor communication register which allows communication of control information between both the central processor and the IOC processor and from the central processor to the peripheral processor over a shared bus.

Abstract: Apparatus for selectively producing at a single output terminal one of a plurality of pulse repetition frequencies (PRF) in response to a set of control signals. After decoding the control signals, the apparatus contains networks for delaying and gating affected clock drive pulse repetition frequencies. Apparatus output is a train of pulses whose PRF varies from time to time, but within a relatively narrow spectrum, under control of the decoded control signals. Such output signals are particularly useful for driving logical components in a computer system with highly specialized and sensitive system specifications.