Abstract: An audio speaker driver having a voice coil with graduated windings such that different sections of the voice coil have different electrical resistances and/or lengths per unit of height of the voice coil. A center portion of the voice coil gives a greater BL, while outer portions give lower overall electrical resistance, such that the audio speaker driver is highly efficient and linear during low excursion operation, with a smoother transition from the linear region to the grossly non-linear region. The wire of the graduated voice coil can have varying cross-sectional area over its length, can be wound on varying on-center spacing, can be wound in different numbers of layers in the various sections, and/or it can fork into interlaced, parallel windings.

Abstract: An electromagnetic transducer such as an audio speaker having at least one of the soft magnetic components of its motor assembly constructed as a laminated structure of electrically insulated magnetically conductive sections. Eddy currents, which would have been induced in a monolithic component in response to an electrical signal applied to the voice coil, are prevented or significantly reduced by the electrical insulation material between the sections of the laminated component. The transducer produces less heat, is less susceptible to flux modulation, and has increased power handling and reduced distortion.

Abstract: A loudspeaker cabinet with a laminated internal brace which has a first rigid layer coupled to a first exterior panel of the cabinet, a second rigid layer coupled to an a second exterior panel of the cabinet, and a damping layer affixed between the rigid layers where they overlap. Vibration, flexure, and expansion/contraction of the cabinet are damped by shearing forces applied to the damping layer as the rigid layers move in opposite, parallel directions.

Abstract: An electromagnetic transducer such as an audio speaker which includes an asymmetric diaphragm to deliver smooth frequency response with reduced distortion by reduction of common modes in the diaphragm. Other benefits such as asymmetric directivity patterns can be realized. The asymmetric cone has a perimeter OD at which a surround may be coupled, and an ID at which a bobbin or spacer may be coupled. The center of the ID is not coincident with the center of the OD. The transducer further includes a stabilization mechanism for reducing rocking of the diaphragm assembly. The stabilization mechanism may include mass balancing of the diaphragm and/or adjustments to the location or symmetry of the suspension components.

Abstract: An output skew detection circuit detects and measures output skew tOSLH, tOSHL between multiple in phase common edge output signals propagated through a multiple signal driver circuit having n outputs. The output skew detection circuit senses common edge output skew across the n in phase output signals simultaneously and directly. A first logic gate has n inputs coupled to the n outputs, detects occurrence of either the first or last of the multiple common edge output signals, and generates a first skew detection edge signal at a first logic gate output. The first and last common edge output signals are the signals propagated with minimum and maximum propagation times tplhmin, tphlmin and tplhmax, tphlmax. A second logic gate has n inputs coupled to the n outputs in parallel with the first logic gate. The second logic gate detects occurrence of the other of the first and last of the multiple common edge output signals and generates a second skew detection edge signal at a second logic gate output.

Abstract: A tristate output buffer circuit provides overvoltage protection from voltage signals on a common bus having a higher voltage level than the internal high potential power rail of the tristate output buffer circuit. A high potential level pseudorail (PV) is coupled to the NWELL of a P channel output pullup transistor (P4). A comparator circuit (P5,P6) couplings the pseudorail (PV) to the output (VOUT). The comparator circuit passgates (P5,P6) are constructed to couple the pseudorail (PV) to the high potential power rail (VCC) for VOUT<VCC and to couple the pseudorail (PV) to the output (VOUT) for VOUT>VCC. A feedback transistor (P1) couples the pseudorail (PV) to an internal node of the tristate output buffer circuit at the control gate node of the output pullup transistor (P4). The feedback transistor (P1) control gate node is coupled to a tristate enable input (EN) for turning on the feedback transistor (P1) during the tristate operating mode and holding off the output pullup transistor (P4).

Abstract: An integrated circuit device ECL test access port (TAP) is constructed for low static current requirements and low power consumption when the TAP is inactive. The ECL test access port may conform with IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture. An SCS logic circuit (50) is incorporated in the TAP controller coupled to the flip-flops (32,34,36,38) of the TAP controller n state finite machine for generating a current sink switch control signal (SCS) according to the state of the TAP controller. A current sink switch circuit (24) is coupled to respective current sinks of ECL gates incorporated in the boundary scan register (BSR/TDR1), design specific TAP data registers (DS/TDRs), TAP instruction register (TIR), and device identification register (DIR/TDR3). The current sink switch circuit (24) has an input coupled to the SCS logic circuit (50) to receive the current sink switch control signal (SCS).

Abstract: A full swing CMOS output buffer circuit (20,30,40,50) isolates incompatible power supply circuits such as 3.3 v standard and 5 v standard subcircuits, and isolates power supply rails of quiet or powered down buffer circuits from the common external bus. The pullup output transistor (PMOS1) is fabricated in a well (NWELL) of N type carrier semiconductor material formed in a substrate (PSUB) of P type carrier semiconductor material. A P channel NWELL isolation switch transistor (PW1) has a primary current path coupled between the well (NWELL) and high potential power rail (VCC) and a control gate node coupled to the control gate node of the pullup output transistor (PMOS1) for operating substantially in phase. The NWELL isolation switch transistor (PW1) isolates the pullup output transistor (PMOS1) well (NWELL) from the high potential power rail (VCC).

Abstract: A lateral PNP transistor structure is fabricated in a BICMOS process utilizing the same steps as are used during the BICMOS process for fabricating NPN and CMOS transistors without requiring additional steps. A base N+ buried layer B/N+BL formed in the IC substrate P/SUB underlies the bipolar PNP transistor. A base Retro NWELL B/NWELL and a base contact Retro NWELL BC/NWELL are formed in the base N+ buried layer B/N+BL using the CMOS Retro NWELL mask, etch and N type introduction sequence. An epitaxial layer EPI of undoped or low doped EPI is deposited across the IC substrate and isolation oxide regions ISOX isolating the PNP transistor are grown during the isolation oxide ISOX mask, etch and grow sequence. The NPN collector sink definition mask, etch and N type introduction sequence is used to form a PNP base contact N+ sink region BC/N+SINK to the BC/NWELL and B/N+BL.

Abstract: A temperature compensated ECL output driver circuit incorporates an ECL output gate (Q4,Q3) coupled between high (V.sub.CC) and low (V.sub.EE) potential power rails with output voltage swing resistors (R2, R1). The ECL output gate provides an output node (N1) at the collector node of one of the ECL output gate transistors (Q4). A first current sink (Q5,R4) is coupled between the common emitter node coupling (N3) of the ECL output gate (Q4,Q3) and low potential power rail (V.sub.EE). A compensating current source (Q11,R5) is coupled to the ECL output gate output node (N1) for generating a supplementary compensating current during operation of the ECL output driver circuit in intermediate and high temperature operating ranges. A compensating current switch (Q9,Q10) is coupled in the compensating current path and is constructed for switching off the supplementary compensating current in a specified low temperature operating range to maintain the logic high output signal V.sub.OH within specifications.

Abstract: A new IC wafer fabrication process provides an improved CMOS active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence particularly applicable for preparation of CMOS transistors in BICMOS wafers. The new gate oxide process reduces the number of process steps and thermal cycles, increases the reliability of the gate oxide layer, and substantially reduces differential stress and thermal stress related structural silicon defects in the epitaxial silicon. The process proceeds by forming a photoresist CMOS active strip mask exposing CMOS transistor active areas, etching and removing the CVD nitride layer over the CMOS transistor active areas, and leaving the EPIOX layer. Further steps include introducing dopant material through the EPIOX layer into the EPI layer of CMOS transistor active areas with the photoresist active strip mask in place and adjusting the threshold voltage V.sub.T of the CMOS transistors.

Abstract: An integrated circuit constructed using exposure and etching steps in an FET fabrication process incorporates electrical lead structures coupled to distributed IC components to compensate for process variation. The electrical lead structure (10,14,16,24,34is composed of an etchable conductive layer constructed in a configuration with graduated coupling widths (B,C,D,E . . . ) forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence. A primary lead (IA) is coupled at a first end to the widest coupling width (B). A plurality of secondary leads (0B,0C,0D,0E . . . ) distributed along the electrically coupled sequence of graduated coupling widths are coupled respectively to the distributed electrical component elements (P1B,P1C,P1D,P1E . . . ) (N1B,N1C,N1D,N1E . . . ) (RB,RC,RD,RE . . . ) of a distributed electrical component such as a PMOS transistor (P1) NMOS transistor (N1) or resistor (R). The graduated coupling widths (B,C,D,E . . .

Abstract: A BICMOS input buffer circuit (20) incorporates an integral CMOS passgate circuit (P2,N2) between bipolar input (Q1) and output (Q3,Q4,Q5) transistors of the input buffer circuit. Latch enable inputs (LE) receive latch enable signals for operating the input buffer circuit and internal passgate in a transparent mode for passing data signals from the input (V.sub.IN) to the output (V.sub.OUT) and in a blocking mode for blocking data signals. The internal CMOS passgate circuit (P2,N2) is coupled into the input buffer circuit (20) to control nodes of the transistor output pullup (Q4,Q5) and pulldown (Q3) for controlling the conducting states of the respective transistor output pullup and pulldown to implement the blocking and transparent modes. A third passgate transistor (P3) may also be coupled between a control node (m1) of the transistor output pullup (Q4,Q5) and the low potential power rail (GND) for positive turn off of the output pullup.

Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction.

Abstract: A circuit to be used with tristate output buffers as a means of diverting from the output pulldown transistor control nodes Miller Current arising while the output buffer is being switched from the low-active state L to the inactive state Z. The circuit complements a DC Miller Killer circuit, relieving the latter from having to deal with this transient, and hence permitting a down-sizing of the DCMK transistor. The net effect is a significantly faster L.fwdarw.Z transition for the tristate buffer and a slightly faster Z.fwdarw.L transition, all accomplished without degrading the DC Miller Killer protection against L.fwdarw.H bus transitions.The key to the present invention is its use of the time interval between the respective, sequential switching of the enable buffer outputs, E and EB following the application of a disable signal to this enable buffer. The present invention includes circuitry which ensures that its Miller Killer transistor is conducting only during the transient associated with the L.

Abstract: An output buffer circuit (10,11) is protected by a short circuit protection circuit (12) from short circuit conditions at the output by detecting occurrence of a short circuit condition of the output (V.sub.OUT) shorted to either the high or low potential power rails (V.sub.CC, GND) and by tristating the output buffer circuit upon detecting the short circuit condition. Detection of a short circuit condition is accomplished by sensing and comparing the respective states of signals at the input (V.sub.IN) and output (V.sub.OUT) and detecting occurrence of an out of state condition between the input and output. If the out of state condition is sensed for a sensing time delay period (tC1, tC2) longer than characteristic propagation delay times (tpHL, tpLH), a short circuit sensing signal (VLO, VHI) is generated.

Abstract: A TTL to CMOS translating input buffer circuit receives TTL input data signals at an input (V.sub.IN) and delivers CMOS data signals at an output (V.sub.OUT). The input buffer circuit is provided with an expanded first stage with expanded pullup circuit (P1) and pulldown circuit (N1) having control gate nodes coupled to the input (V.sub.IN). The pullup and pulldown circuits (P1,N1) are constructed to provide dual switching thresholds at the input (V.sub.IN). A first stage output pullup and pulldown circuit (P1R,P1L,N1L) switches at a relatively lower first threshold voltage level. A pullup enhancer circuit (P1E,I3,I4) switches at a relatively higher second threshold voltage level. The pullup and pulldown circuits (P1,N1) of the expanded first stage are constructed for switching dynamic current at an output node (m1) at the relatively lower first threshold voltage level for data signal transitions between high and low potential levels at the output node (m1).

Abstract: Apparatus (10) and method for solder finishing the leads of an integrated circuit package are applicable to "flat packs" or flat packages having coplanar rows of leads (84) along sides of the flat package (75). First and second tracks (22,26) are formed with elongate first and second supporting surfaces (72,74) oriented with the first and second supporting surfaces at opposite first and second downwardly depending angles (.THETA.1,.THETA.2). First and second index edges (70) are formed along the respective first and second supporting surfaces of the first and second tracks (22,26) for retaining a flat package (75) at the respective opposite first and second downwardly depending angles. Vertical first and second falling columns of molten solder are established at first and second loci of solder finishing (16a,16b) defined by solder bridge sections (66,68) with the first and second falling columns (85) located on the lower sides of the respective first and second tracks (22,26).

Abstract: A contact test structure and method provide accelerated testing of long term reliability of metal to silicon ohmic contacts and adjacent PN junctions on IC dies of a wafer. At least one wafer level reliability contact test structure (10) is formed on the wafer during CMOS or BICMOS wafer fabrication mask sequences without additional steps. A shallow layer (N+S/D) of semiconductor silicon material of second type carrier (N) conductivity is formed in a well (PWELL) of first type carrier (P) conductivity silicon material with a shallow PN junction (J) between the shallow layer and well. Metal to silicon first and second test contacts (TC1,TC2) of metal layer portions (M1) are formed at first and second locations on the shallow layer (N+S/D) spaced apart a selected distance. The second test contact (TC2) has a contact area between a metal layer (M1) and shallow layer (N+S/D) in the minimum size range for the fabrication process for maximizing current density through the second test contact (TC2).

Abstract: A BICMOS output buffer circuit delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). A CMOS output pulldown driver transistor (Q60) sources base drive current to a relatively large current conducting bipolar primary output pulldown transistor (Q44). A relatively small current conducting CMOS secondary output pulldown transistor (Q60A) is coupled with primary current path in parallel with the primary current path of the bipolar primary output pulldown transistor (Q44) between the output (V.sub.OUT) and low potential power rail (GNDN). The control gate node of CMOS secondary output pulldown transistor (Q60A) is coupled to the control gate node of the CMOS output pulldown driver transistor (Q60) to initiate pulldown of a small sinking current before turn on of the bipolar primary output pulldown transistor (Q44) to reduce the maximum peak output noise (V.sub.OLP).