Abstract: A skew tester (60) measures output timing skew parameters OSHL and OSLH between multiple output signals of an integrated circuit (IC) device under test (DUT) having an input and multiple outputs. A measurement signal generating circuit (15,16,18,20) generates a square wave measurement signal at a test signal frequency synchronized with a clock signal. The measurement signal generating circuit uses direct digital synthesis to provide a specified phase shift resolution. A test signal generating circuit (15,22,24) generates a square wave test signal at the test signal frequency using the same clock signal. The test signal and measurement signal are therefore synchronized in frequency. The test signal is applied to the input of a DUT (25) and a switch (30) selects one of the DUT output signals.

Abstract: A programmable and controllable timing circuit (CTC) is formed on an integrated circuit chip (IC) having a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin, a TAP data output (TDO) pin, a TAP mode select (TMS) pin, and a TAP clock (TCK) pin. The test access port includes a plurality of TAP data registers (TDRs) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin. A TAP instruction register (TIR) is coupled to receive instruction codes at the TDI pin and to direct use of selected TDRs. A TAP controller is coupled to receive control signals at the TMS pin and clock signals at the TCK pin and provide control and clock signals for controlling operation of the TIR and TDRs. The TAP is provided with a controllable timing circuit design specific TAP data register (CTC/DS/TDR) constructed for receiving a coded CTC digital timing code at the TDI pin.

Abstract: A circuit to be used with bistate and tristate output buffers as a means of diverting from the output pulldown transistor Miller Current arising while the output buffer is powered down. Its purpose is to avoid loading the common bus to which the output buffer is attached, in particular under the circumstances where other output buffers on the bus are causing transitions to occur and the buffer of interest has been powered down. In its preferred embodiment the invention utilizes a MOS transistor coupled between the output pulldown transistor and the lower potential power rail of the output buffer. This MOS transistor is controlled by another MOS transistor coupled to output V.sub.OUT of the buffers. This driver transistor is controlled by the high potential power rail of the buffer and so turns on the Miller Current Discharge Transistor only when the buffer is powered down. The invention also encompasses a discharge transistor coupled to the data input V.sub.

Abstract: An edge controlled output buffer circuit reduces the amplitude of power rail noise while maintaining high switching speed by controlled storage and release of charge at the output using new charge storage and discharge capacitor circuits coupled to the output. An output discharging storage capacitor (C1) is coupled to the high potential power rail (V.sub.CC). A first passgate circuit PSGT1 is coupled between the charge storage capacitor (C1) and the output (V.sub.OUT). A first control circuit (CTR1) is coupled to the control node (m2) of the first passgate circuit (PSGT1) for transient turn on of the first passgate circuit (PSGT1) when the output is still at high potential level during transition from high to low potential level at the output. A second passgate circuit (PSGT2) is coupled between the charge storage capacitor (C1) and the low potential power rail (GND).

Abstract: In a BiCMOS TTL output buffer circuit, bipolar output pullup and pulldown transistors (Q3,Q4,Q5) source and sink current at an output (V.sub.OUT). A phase splitter transistor (Q2,N4) is coupled to the bipolar output pullup and pulldown transistors for controlling respective conducting states in response to data signals at an input (V.sub.IN) during the active bistate mode of operation. CMOS tristate transistors (P1, ,P2,P4,N2) form a tristate circuit for implementing an inactive tristate mode at the output V.sub.OUT in response to tristate enable signals at a tristate enable input (OE). In order to reduce quiescent input current (I.sub.CC) power dissipation, an input power switch CMOS transistor (NI,N4,P1A) is coupled in the input current path to the high potential power rail (V.sub.CCI). The control gate node of the input power switch CMOS transistor (N1, ,N4,P1A) is coupled to the input (V.sub.IN) to control sourcing of input current (I.sub.

Abstract: An output buffer circuit (10) delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (V.sub.CCQ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (V.sub.CCN) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (V.sub.CCQ, V.sub.CCN) for reducing V.sub.CC droop in the relatively noisy supply rail (V.sub.CCN) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (V.sub.OUT). A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN).

Abstract: A V.sub.OH clamp circuit reduces propagation delay time TP.sub.HL and reduces ground bounce noise in TTL output buffer circuits. First and second band gap bias generators (BG1,BG2) coupled in series provide a substantially stable clamp reference voltage level (V.sub.R) over a specified range of operating temperatures. The clamp reference voltage level (V.sub.R) is referenced to the low potential power rail (GND). Voltage drop components (D32,QC) of the Y.sub.OH clamp circuit couple the reference voltage level (V.sub.R) through the voltage drop components (D32,QC) to an internal node, namely the base node (BDAR) of the pullup Darlington configuration transistor pair (Q12A,Q12B), The V.sub.OH clamp circuit clamps the high potential level output signal (V.sub.OH) at a maximum voltage level (V.sub.OHMAX) less than the high potential level power rail (V.sub.cc), and referenced to the clamp reference voltage level (V.sub.R).