Abstract: A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system.

Abstract: A field is defined in branch instructions which is interpreted by software as “Hint” bits and these bits are used to signal the processor of special circumstances that may arise when doing speculative branch instruction execution to enable better branch address prediction accuracy and a reduction in link stack corruption which improves overall execution times. A programmer or compiler determines if a branch instruction usage fits in the context for a Hint action. If so, the compiler or programmer, using assembly/machine language, sets Hint bits in the branch instruction when it is compiled. If the branch is later speculatively executed, the processor decodes the Hint bits and executes and a hardware action corresponding the decode of the Hint bits. These Hints include four specific Hint actions, however, the field reserved for Hint bits is five bit wide reserving up to thirty-two specific Hint cases may be specified.

Abstract: A voltage controlled oscillator (VCO) is constructed using a series ring connection of an odd number K of logic inverters where K is greater than three. Each sequence of three of the logic inverters has voltage controlled feed-forward conduction circuit coupled in parallel. Each of the feed-forward circuits has the same phase between its input and output as the path it parallels. The control voltage of the feed-forward circuits operates to decrease the path delay of the logic inverters when they are conducting. Selectable inverters are connected in parallel with each logic inverter using a P and an N channel field effect transistor (FET). The N channel FET is controlled with a Mode signal and the P channel FET is controlled by a Modeb signal which is generated by inverting the Mode signal. The Mode and Modeb signals control the connection of the selectable inverters are in parallel with the logic inverters thus increasing the drive capability of the parallel combination of inverters.

Abstract: A trace array for recording states of signals includes N-storage locations for k trace signals. In the write mode, an address generator combines the outputs of an event signal counter and a cycle clock counter to generate trace array addresses. A start code is written each time an event signal occurs and event addresses are saved. Recording is stopped by a stop signal and the stop address is saved. A compression code and time stamp code are written when no state changes occur in any trace signals at the cycle clock times to compress recorded trace signal data. An output processor reads out stored states of the trace signals and uses the start codes, event addresses, stop address, compression code and time stamp to reconstruct the original trace signal sequences for analysis.

Abstract: An induction generator having one or more energy windings and one or more auxiliary windings where the auxiliary windings have fixed and switched capacitors which are used to control the induction generator output under variable load conditions. The auxiliary windings are electrically and magnetically isolated from the energy windings. The fixed capacitors are used under minimum load condition and the switched capacitors added in response to controls signals. The control signals are determined by analyzing the load voltage and current and the voltage across the particular capacitor being added. The induction generator is included in systems where the generator is rotationally driven by an engine and which couples the energy windings to a power grid and/or to a variable load. The engine may also employ a controller that receives the load current and voltage signals to determine engine speed.

Abstract: A method and systems for projecting an image onto a screen in high ambient light. The image is composed as pixels comprising selected intensities of preselected bands of visible light. The pixels are created by modulating three frequencies of light corresponding to hues in the red, green, and blue spectrum. The modulated light selectively generates pixels of a frame of the image. A diffusive projection screen has a triple bandpass light filter surface that selectively transmits preselected bands of light frequencies around the red, green, and blue spectrums of the modulated light source. The triple bandpass light filter is used with projection screens in front and rear projection systems. The hues of red, green, and blue may be generated from LEDs or from extracting the frequencies from a broadband source. The modulator system may comprise a time multiplexed single modulator design or a triple modulator design.

Abstract: In a system where a path history vector is used in conjunction with a branch history table, an algorithm is disclosed for reducing the number of bits required for a path history vector. The path history vector is used to address a branch history table. Since the path history vector may contain a large number of zeros, this may lead to branch predictions that are inaccurate because of the limited size of the path history vector and the corresponding branch history table. A compression algorithm is disclosed where zeros in the path history vector are compressed. The number of zeros greater than one but less than a maximum are compressed in a single zero. With a compressed path history vector, inner loops with larger iterations or loops with larger instructions or branches are predicable with greater accuracy.

Abstract: A writeable K by P trace array with parallel inputs and outputs is incorporated within a VLSI integrated circuit. The trace array is partitioned into N sub-arrays each sub-array having M=P/N entries for the K input signals. Logic circuitry couples selected K input signals to the trace array so that M states of the K input signals may be stored in each of the N sub-arrays. A start signal enables storing of states of the K input signals at time intervals determined by a clock. The clock is counted in a counter and when M is reached the counter is reset back to an initial state. New states of the K input signals written over old states until a pre-determined event signals occurs, at which time storing the sub-array is stopped saving the stored states of the logic inputs. Writing is simultaneously started in a succeeding sub-array in the same fashion until another event signal occurs.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a plurality of dynamic logic circuits each performing a Boolean function on a plurality of inputs and generating an output on a dynamic node. The corresponding plurality of dynamic outputs are coupled to a static logic circuit which performs an additional Boolean function of the plurality of dynamic outputs. The static logic circuit operates to generate an output logic state that is maintained so long as the value of the Boolean operations being performed by the logic device do not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element.

Abstract: A system for transmitting and receiving data between the near end to the far end of a transmission line. The system has simultaneous bi-directional (SBIDI) drivers and receivers for high performance over well behaved transmission lines. The SBIDI drivers and SBIDI receivers are enabled and disabled by logic inputs. A unidirectional (UNI) receiver is connected in parallel with each SBIDI receivers. Logic insures that the SBIDI and UNI receivers are not enabled at the same time. When desired, the SBIDI receivers are disabled and the UNI receivers enabled and signaling is done unidirectional. The current level in the SBIDI drivers may be modified in response to mode compensation signals to improve signal to noise in the unidirectional mode and to compensate for losses in the simultaneous bi-directional mode. The system may be integrated into all I/O's for maximum design flexibility.

Abstract: A composite fabric is made from a fabric layer which has one or more expandable bladders coupled at spaced intervals across the surface of the fabric layer and extending substantially transverse to said spaced intervals a bladder length across the surface of the fabric layer. The expandable bladders are attached by threading them through fabric loop attached to the surface the fabric layer. The expandable bladders are coupled to an air source with air valves and selectively inflated and deflated. As the expandable bladders are inflated and deflated, they selectively cover and uncover area adjacent to their corresponding bladder lengths. The expandable bladders may be formed in various configurations and the fabric loops may or may not be stretchable. The composite fabric may be used to construct fabric products with various functional shapes where the thermal insulation across one or more surface areas of the fabric products are varied.

Abstract: A method and system for testing an integrated circuit (IC) comprising a plurality of logic units and a plurality of level sensitive scan design latches (LSSD) chains (scan chains) where the partitioning of the scan chains is different than the partitioning of the logic units. Scan blocks, each scan block comprising multiplexers, a pseudo random pattern generator (PRPG), a partitioned multiple input shift register (MISR), functional logic and control function logic are distributively placed around and close to scan inputs and scan outputs of the IC in otherwise unused area too small for larger functional logic blocks. The MISR, which contains many loaded latches and other logic, would normally be the largest element of the scan block has been partitioned into a sub-set of a full MISR to minimize the size of an individual scan block.

Abstract: Testing register bits and in particular bitmask registers is a method employed in many computer architectures (e.g., IBM PowerPC, IA32, VAX, etc.) to manage instruction flow within a processor. Since the testing or scanning of bitmask registers for the first occurrence of a logic state (e.g., logic one) is done quite often, register scanning is implemented in hardware in these processors. Other computer architectures (e.g., Intel IA64) manage instruction flow with alternate methods and therefore do register scanning as a software construct. When software written for the first computer architecture (e.g., IBM PowerPC) is ported to a system with IA64 architecture, the program would execute with reduced speed. The IA64 architecture uses the EPIC instruction protocol and as such executes predicate instructions that employ a predicate register where each bit of the predicate register can be associated as the true or false result of a comparison.

Abstract: The present invention discloses a method of managing lists in a multiprocessor system without the use of locks that prevent contention for the list. List management in a linear list with a front and a back of the list has applications where it is desirable to manage the list in a Last In First Out (LIFO) and a First In First Out (FIFO) or a combination of LIFO and FIFO. LIFO and FIFO list management can be done by restrictively adding data elements to the front, back and removing data elements from the front of a managed list. At certain times there can be contention for a list and either locking routines are in place to prevent contention or some other method is used to guarantee data element integrity. The present invention discloses a set of operations that when used with certain protocols allow two or more processors to access a list as a LIFO or FIFO in a multiprocessor system without the use of locks.

Abstract: A method for automatically running a plurality of interactive programs that are necessary to complete a VLSI design and verification is disclosed. Layout data is completed and saved. Multiple programs of the VLSI logic are launched using this data. The submission of design programs (jobs) operate as program “states” with each program state having data inputs, data outputs possibly receiving logic inputs and generating logic outputs. The data inputs and data outputs may be conditional in that they were generated from other program states that may not have executed error free. Logic routines generate the logic signals which are logic combinations of the generated logic outputs and these logic signals may be used to launch other program states. Once the method is started, a designer simply corrects errors that occur and then re-starts the design process.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: A Schematic database defining a Schematic is checked and saved. Multiple programs affected by the Logic of the VLSI Schematic are launched along with a Checking program that extracts data related to the Logic of the VLSI Schematic design and other data that may be necessary but is not related to the Logic of the VLSI Schematic design. The Schematic design programs operate as executable program states with each program state having program data inputs and outputs and program logic inputs and outputs. Once the method is started, a designer simply corrects errors that occur and then restarts the Schematic design process. If changes in the Schematic database do not affect the Logic then Logic related programs states are stopped and programs for correcting non Logic related changes are run. Program output data may be conditional with errors or unconditional without errors depending on operational modes.

Abstract: The present invention discloses a method and system for testing imbedded logic arrays. An imbedded logic array is first tested for read/write functionality and then a test sequence is run to test the imbedded logic function. The method of the present invention writes a first data pattern to all addresses in an imbedded logic array. Next a second data pattern is written to a specific address followed by a read selecting all addresses concurrently. The output of the imbedded logic array, during this test, is the logic combination of the first data pattern and the second data pattern at the address where the second data pattern was written. By comparing the imbedded logic array output to an expected output the imbedded logic of the array is tested. The present invention anticipates imbedded logic arrays where the expected data output is not a previously written pattern.

Abstract: The present invention adds a programmable expect generator (PEG) that generates expected patterns of output for comparison to the actual outputs of an array while undergoing a complex test input sequence. The output of a programmable array built-in self test (PABIST) controller has its output increased to include separate control bits and a mask bit for a PEG. The PEG in one embodiment of the invention is substantially similar to a data control register that is programmed by a sequence of commands to generate the array input data patterns for testing an array. The program sequence that controls the PABIST and generates the input address, data and read/write patterns also outputs separate control bits to direct the PEG to generate expected outputs from the array when data from corresponding read addresses are read. The incorporation of a mask bit that accompanies each group of PEG control bits is used to inhibit the compare function that compares the output of the array to the output of the PEG.