Abstract: The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by design to allow an instruction to execute and simultaneously to be stored and forwarded to shared memory operable as a trace buffer. Since each processor is general purpose, the trace routine necessary for tracing, can by one of the routines or programs that can be written and executed on either of the processors. One of the processors can run, collect and analyze the executed and store instructions of the other processor. Since the processors can be on a single chip the shared memory bus that writes and reads the executed instructions can operate at high speed.

Abstract: A charge pump has two charge pump nodes. The first charge pump node has a first current source (CS) with a source terminal connected to a positive supply voltage and an output terminal connected to the first charge pump node with a P channel metal oxide silicon transistor (PFET) controlled by a first control signal. The first charge pump node is also connected to a second CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a second control signal. The second charge pump node has a third CS with a source terminal connected to the positive supply voltage and an output terminal connected to the second charge pump node with a PFET controlled by a third control signal. The second charge pump node is also connected to a fourth CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a fourth control signal.

Abstract: The present invention discloses a combination media and media station storage unit for storing a multiplicity of media elements along with a media station for the media elements. The combination unit allows a media station to be stored and secured for protection while allowing connections for signals and allowing controls for the media station to be accessed while it is in a stored and secure position. The combination media and media station storage unit also has removable lids that may contain optional features for adding functionality to the combination media and media station storage unit. These features include but are not limited to speakers, electronics for remote broadcast of playback information, electronics for remote control of the media station, batteries, windows for observing media station status, etc.

Abstract: A phase locked loop (PLL) circuit uses a programmable frequency divider (PRFD) to generate a feedback clock from the PLL output clock. The PLL power supply voltage and a PLL reference current are generated by regulating the scalable logic supply voltage of the system in using regulator circuits. The PLL power supply voltage is regulated to a level lower than the lowest level of the scalable logic supply voltage used by the system. The PLL generates a PLL output clock whose frequency is higher than the highest frequency of operation of the system using the highest level of the scalable logic power supply voltage. The PLL output clock is divided is a second PRFD to generate a divided PLL clock. The PLL clock and a fixed auxiliary clock are selected in a glitch-free multiplexer (MUX) as the system clock for the system. The system clock frequency may be dynamically scaled by programming the divisor in the second PRFD dividing the PLL clock.

Abstract: A glitch-free clock selector selects between asynchronous clock signals. In one embodiment a select signal has two logic states corresponding to the two clock signals. A clock output signal is gated with a latched compare signal which compares a new select signal state to a stored current select signal state. A multiplexer (MUX) selects between the two clock signals in response to a select latch output signal. If the new and current select signals do not compare the clock output signal is forced to a logic zero by the output of a compare latch which latches the compare signal when the MUX output (present selected clock signal) goes to a logic zero. While the present clock signal is held low, the MUX switches to the new clock signal. The new clock signal (MUX output) latches the new select state as the current select state causing the new and current select signal to compare.

Abstract: A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

Abstract: A clock divider circuit receives a first clock signal and frequency divides the first clock signal to generate a second clock signal. The first and second clocks are inputs to multiplexer (MUX) that selects one of the clocks as the MUX output based on the state of a MUX control signal. The MUX output is combined with a latched Freeze clock signal in an AND gate to generate a clock output signal. The state of Bypass logic signal determines which clock signal is selected as the clock output signal. The Bypass logic signal is received in a latch circuit which latches the Bypass logic signal in two series latches one latch latching on the positive edge and one on the negative edge of the MUX output. The output of the second latch is latched in a third latch on when a NOR logic gate signals the first and second clock are concurrently at a logic zero assuring that the MUX output is changed only when both clocks are low. The clock output signal is gated with the latched Freeze clock signal in the AND logic gate.

Abstract: The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate voltage which controls the frequency of the MVCO and to generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: The present invention discloses a microprocessor bus structure that enables a processor chip to be designed with optional unidirectional or bi-directional I/O buses. The processor is designed with separate input and output bus internal to the chip. A gating network is coupled to these processor uni-directional busses that allows the chip to have an alternate externally wired bus structure. For the lowest cost and lowest performance only one set of bidirectional bus lines are wired external to the chip. These lines have a parallel driver and receiver with appropriate gating to allow the bus to be either in the send or receive mode. The signals from the processor uni-directional input and output buses are wired via appropriate gating to create a single bi-directional bus.

Abstract: The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

Abstract: A media storage unit is made by z-folding either a joined or a continuous web of material planes forming a plurality of N overlaid material planes. The material planes have tabs extending from both non-folded sides symmetrical about a center line of each material plane. Slits are made starting on each non folded side and extending a length towards the center of each material plane. The two slits on each material plane are made at the mid-point of the material planes between the tabs allowing the tabs be separated. Opposing tabs on each side of the overlaid material planes and closest to a folded side are joined with a corresponding tab on a adjacent overlaid plane, the opposing tabs are deflected and joined in opposite directions. The joined tabs become the retaining side members of a plurality of pockets formed by the overlaid material planes. The folded sides become the bottoms of sequential pockets with openings in opposite directions.

Abstract: A dynamic logic system is disclosed that uses transmission gates coupled between the inputs and output of inverting CMOS logic gates creating a “vented” CMOS logic gate (VCMOS). A clock is used to turn the transmission gates on during a pre-charge or “vent” cycle which causes the inputs and output of the VCMOS to go to an intermediate or vented state between a logic one and a logic zero. During an evaluation phase, inputs are applied to the VCMOS gate which will evaluate to a logic one or zero depending on the states of the inputs and the logic of the VCMOS gate. A family of vented CMOS gates are constructed by adding transmission gates in series with inputs or outputs to create input VCMOS (IVCMOS) and output VCMOS (OVCMOS) which are used to construct vented dynamic logic blocks (VDLB). A VDLB comprises groups of VCMOS gates which may be vented and isolated from other gates during venting.

Abstract: A video source provides information to a communication device that results in an icon being displayed on the communications device during a preview of a television program or segment of a television program. The icon indicates to the user that a single button on a remote control or other user-controller device can be used to program the communication device, including television, video-cassette recorders, cable boxes, network computers, or the like, to display or record the desired program or program segment as the program segment is being televised or communicated. Specifically, during operation, the exact date, time, and source of the actual television program or program segment is encoded in an unused portion of a teletext data stream when the icon is present. If the communication device receives an appropriate command from its user-controlled device while the icon is displayed, a central processing unit within that communication device, saves the information together with a channel presently being viewed.

Abstract: An IC device bum-in system and method where a burn-in test motherboard is configured with a circuit environment like a customer level system motherboard. A stress software program is executed in a test controller which controls operational parameters to each IC device as well as determining whether an IC device runs system code or Built In Self Test (BIST) code. Running system or BIST code causes self heating which elevates the temperature levels for each IC device. Individual cooling means comprising cooling fans or thermoelectric coolers are used to control IC device temperatures to a desired burn-in level and to set temperature profiles. The stress software program may also adjust other operational parameters to the IC devices during a bum-in cycle. During a system level burn-in test the IC devices may undergo individual bum-in operation parameter profiles depending on the IC device part number.