Abstract: A real-time passive acoustic source localization system for video camera steering advantageously determines the relative delay between the direct paths of two estimated channel impulse responses. The illustrative system employs an approach referred to herein as the “adaptive eigenvalue decomposition algorithm” (AEDA) to make such a determination, and then advantageously employs a “one-step least-squares algorithm” (OSLS) for purposes of acoustic source localization, providing the desired features of robustness, portability, and accuracy in a reverberant environment. The AEDA technique directly estimates the (direct path) impulse response from the sound source to each of a pair of microphones, and then uses these estimated impulse responses to determine the time delay of arrival (TDOA) between the two microphones by measuring the distance between the first peaks thereof (i.e., the first significant taps of the corresponding transfer functions).

Abstract: An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

Abstract: A method and apparatus for performing double-talk detection in an acoustic echo canceller in which a detection statistic is advantageously computed based on an estimate of a cross-correlation between the far-end signal and the return signal which has been normalized with use of an estimate of a covariance matrix of the far-end signal. The estimate of the cross-correlation between the far-end signal and the return signal may be further normalized with use of either an estimate of a variance of the return signal or an estimate of a covariance matrix of the return signal. In certain illustrative embodiments of the invention, one or more of these quantities may be estimated based on signal samples sampled over a predetermined time window. And in another illustrative embodiment of the present invention, the coefficients of the adaptive filter employed in the acoustic echo canceller itself are advantageously used to compute the detection statistic.

Abstract: Two or more digital signals are encoded using two or more respective line codes. The line codes are chosen in conjunction with the data rates of the digital signals such that the encoded signals are substantially orthogonal to each other in the frequency domain. As such, the two or more encoded signals may be combined and transmitted via a single physical medium with little or no interference. A transmitter for encoding and transmitting the digital signals contains line coders for encoding the digital signals and a combiner for combining the encoded signals for transmission via a single physical medium. A receiver for receiving and decoding the combined encoded signal contains filters for extracting the individual encoded signals and line decoders for decoding the individual encoded signals to generate the original digital data signals.

Abstract: A method and apparatus for coding and decoding a sequence of data packets with use of a novel class of forward error correcting codes having coding rates greater than 1/2 which nonetheless provide relatively high levels of channel protection against burst erasures with a relatively low decoding delay. In accordance with certain illustrative encoder embodiments of the present invention, the source information contained in each of a plurality of packets to be coded is similarly divided into a plurality of (similar) corresponding portions, and “checksums” are computed over multiple data packets, each such checksum being based on different (i.e., non-corresponding) portions of at least two of the multiple packets. These “checksums” are then advantageously appended to various subsequent data packets to be coded.

Abstract: A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material.

Abstract: A micro-electro-mechanical system (MEMS) actuator device is disclosed. The MEMS actuator device has an actuated element that is rotatably connected to a support structure via torsional members. The torsional members provide a restoring force to keep the actuated element planar to the surface of an underlying substrate. The surface of the substrate has electrodes formed thereon. The electrodes are adapted to receive an electrical potential. When an electrical potential is applied to certain of the electrodes, an electrostatic force is generated which causes the actuated element to rotate out of plane. The electrodes have three components. At least a portion of two of the components is within the tilting area of the actuated element. The third is outside the tilting area of the actuated element. The tilting area is defined as the surface area of the actuated element as projected onto the underlying substrate.

Abstract: A process for fabricating trench capacitors in an interconnect layer of a semiconductor device is disclosed. In the process, at least one interconnect is formed in the interconnect layer, which is then planarized. To form the trench capacitor, a trench is formed in the dielectric material of the interconnect. The bottom of the trench communicates with a metal contact in the underlying layer. A barrier layer of material is formed on the interconnect layer and is anisotropically etched, leaving the barrier layer on the sidewalls of the trench. The lower plate of the capacitor is then formed by depositing a layer of metal over the interconnect layer. The layer of metal is then anisotropically etched, removing the metal on the surface of the interconnect layer and leaving the metal along the trench perimeter. The capacitor dielectric layer is then deposited over the interconnect layer and subsequently patterned. Another layer of barrier material is deposited on the interconnect layer.

Abstract: A semiconductor device in which hole-induced damage to the dielectric layer is reduced is disclosed. In the device, a layer of a conductive, high bandgap (i.e. a material with a bandgap greater than 1.1 eV) material is formed adjacent to the dielectric layer. The presence of the high bandgap material reduces the hole-induced damage to the dielectric layer that occurs during device operation compared to devices in which the conductive material adjacent to the dielectric is silicon.

Abstract: A process for the metalization of substrates is disclosed. The metal either forms a coating over the entire substrate, or it is patternwise deposited on the substrate surface. Metal is patternwise formed on the substrate either by forming a pattern of resist material on the substrate and depositing the material in the interstices defined by the pattern or by forming a patterned resist layer over a metal layer and transferring the pattern into the substrate using conventional techniques. The patterned resist layer is formed on the substrate using conventional techniques. The substrate is treated with reagents that promote the electroless plating of metal on the substrate surface. If the resist material has been previously formed on the substrate surface, the substrate surface is then dried. The remaining resist is then removed from the substrate surface.

Abstract: A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

Abstract: A method of fabricating a semiconductor device having a gate dielectric layer. The method includes the step of ion implanting at least one of Zr, Hf, La, Y, Al, Ti and Ta into the gate dielectric layer at low implant energy level to increase the dielectric constant of the dielectric layer. Subsequently, the implanted gate dielectric layer is annealed.

Abstract: An improved PIN photodiode provides enhanced linearity by confining the light absorption region of the diode wholly within the depletion region. The photodiode exhibits improved linearity over prior art designs because the thickness of the absorption region is no longer a function of changes in the size of the depletion region during device operation. Keeping the absorption region wholly within the depletion region ensures that the charge carriers generated by incident illumination will increase the conductivity of the semiconductor material.

Abstract: A process for forming a metal oxide or a metal silicate gate dielectric layer on a semiconductor substrate is disclosed. A suitably prepared substrate is placed in a chamber. An organic precursor gas is flowed into the chamber. An inorganic precursor gas is then flowed into the chamber. The organic precursor gas catalyzes a reaction between itself, the inorganic precursor and the substrate to form a dielectric layer on the substrate.

Abstract: We have found that a single crystal, single domain oxide layer of thickness less than 5 nm can be grown on a (100) oriented GaAs-based semiconductor substrate. Similar epitaxial oxide can be grown on GaN and GaN-based semiconductors. The oxide typically is a rare earth oxide of the Mn2 0 3 structure (e.g., Gd2O3). The oxide/semiconductor interface can be of high quality, with low interface state density, and the oxide layer can have low leakage current and high breakdown voltage. The low thickness and high dielectric constant of the oxide layer result in a MOS structure of high capacitance per unit area. Such a structure advantageously forms a GaAs-based MOS-FET.

Abstract: A method and apparatus for estimating channel impulse response and data in a signal transmitted over a channel in a communication system. The channel impulse response is estimated uses correlative channel sounding, and then, using the estimated channel impulse response, the data in the signal is estimated. The output is then fed back to the channel impulse response estimator and the channel impulse estimation is repeated. The data estimation and channel impulse response estimation may be iterated a number of times.

Abstract: An apparatus for projection lithography is disclosed. The apparatus has at least one magnetic doublet lens. An aperture scatter filter is interposed between the two lenses of the magnetic doublet lens. The aperture scatter filter is in the back focal plane of the magnetic doublet lens system, or in an equivalent conjugate plane thereof. The apparatus also has two magnetic clamps interposed between the two lenses in the magnetic doublet lens. The clamps are positioned and configured to prevent substantial overlap of the magnetic lens fields. The magnetic clamps are positioned so that the magnetic fields from the lenses in the magnetic doublet lens do not extend to the aperture scatter filter.

Abstract: A process for forming a semiconductor wafer with a flat surface is disclosed. In the process, a bare semiconductor wafer that has been sawed from an ingot is provided. A layer of planarization material is formed on at least one major surface of the semiconductor wafer. The layer of planarization material is placed into contact with a respective object having a flat surface. Pressure is applied to cause the planarization material to flow and impart a planar, surface to the layer of planarization material. The planarization material is then hardened. The flat surface is separated from contact with the respective layer of hardened material. The surface flatness is then transferred into the underlying substrate surface.

Abstract: A micro-electro-mechanical optical device is disclosed. The micro-electro-mechanical optical device includes a micro-electro-mechanical structure coupled with an optical device. Both the micro-electro-mechanical structure and the optical device are disposed on a substrate surface. The micro-electro-mechanical structure lifts the optical device a predetermined distance above the plane of the substrate surface. Thereafter, the lifted optical device is moveable relative to the plane of the substrate surface in response to an electrostatic field generated between the optical device and the substrate.

Abstract: A process for fabricating a semiconductor device with copper interconnects is disclosed. In the process of the present invention, a layer of dielectric material is formed on a substrate. A barrier layer to prevent copper diffusion is then deposited over the entire surface of the substrate. A dual copper layer is formed on the barrier layer. The dual layer has a copper layer deposited by PVD and a copper layer deposited by electroplating. The copper layers are adjacent to each other. The ratio of the thickness (X) of the electroplated, layer to the thickness of the PVD layer (Y) is about 1:0.5 to about 1:2. The thickness of the electroplated layer is at least about 3 &mgr;m. The thickness of the PVD copper layer is at least about 100 nm. The thickness of the two layers is selected to effect recrystallization of the electroplated copper from a small grain size (0.1 &mgr;m to 0.2 &mgr;m) to a large grain size (1 &mgr;m or greater).