Abstract: A novel Finite Impulse Response filter (FIR) Filter is provided which includes a plurality of multipliers (14-22), a plurality of multiplexers (24-32), and a plurality of sample and hold circuits (34-42). At least two of the sample and hold circuit output signals (1-5) may be multiplexed in a round robin fashion to at least two of the multipliers (14-22). The multipliers may receive as a second input, fixed tap coefficient signals (C.sub.1 -C.sub.5) for multiplication with the multiplexed sample and hold circuit output signals (1-5).

Abstract: An trace analyzer apparatus and method useful in semiconductor processing for measuring trace impurities in gases and liquids comprising a gas chromatograph serving to replace a bulk gas in a composition of bulk gas including contaminants in a bulk gas stream with a carrier gas having a higher ionization potential than that of said contaminants, where such gas chromatograph is connected to a hollow electrode (14) for initiating ionization of said contaminants by electrical discharge, where such electrode is electrically isolated from a source housing (44) and adjacent to a skimmer plate (16) that ionizes trace contaminants that are measured using a mass spectrometer, is disclosed.

Abstract: A method is described to control the maximum density and the pixel profile of microdots produced by a binary or multilevel electrophotographic device. In various embodiments, from the maximum development potential. The working point of the device is established by imposing a relation between charge level, discharge level and saturation voltage level of the photosensitive element. This allows to achieve consistent output densities, irrespective of the environmental parameters, such as relative humidity and temperature.

Abstract: A capacitive structure on an integrated circuit and a method of making the same are disclosed, which is particularly useful in random-access memory devices. Generally, the method of the present invention comprises the steps of forming a substantially vertical temporary support 54 (preferably by forming a cylindrical aperture in an insulating layer) on a semiconductor substrate 10 and forming a substantially vertical dielectric film 32 (preferably a high dielectric constant perovskite-phase dielectric film, and more preferably barium strontium titanate) on temporary support 54. The method further comprises depositing a first conductive (e.g. platinum) electrode 60 on substantially vertical dielectric film 32, and subsequently replacing temporary support 54 with a second conductive (e.g. platinum) electrode 64, such that a thin film capacitor 44 which is substantially vertical with respect to substrate 10 is formed.

Abstract: A RTP system and method. A first lamp zone (108) is located around a periphery of a wafer (102) for heating the center of the wafer (102) and a second lamp zone (114) is located around the periphery of the wafer (102) for heating the edge of the wafer (102). The chamber (104) includes highly reflective surfaces (106). Light from the first and second lamp zones (108, 114) is reflected off of the highly reflective surfaces (106) at least three time before reaching the wafer (102). Thus, the wafer (102) is isotropically heated and uniform wafer heating is achieved.

Abstract: A socket (1) for removably receiving semiconductor devices (8) for testing purposes has film contacts (81) each having a continuous or discontinuous annulus (71, 73, 76, 78) that has been formed on a film substrate and with a recess (72, 74, 77, 79) formed within the annulus exposed at a bottom of a seating or accommodating portion (31). When a BGA type semiconductor device (8) is received in the accommodating part (31) and a cover (16) is closed, electrically conductive balls (9) on the bottom of the semiconductor device (8) are pressed against respective film annular contacts (81, 82, 83, 84) thereby effecting an electric connection. Since the bottom most portion of the electrically conductive balls (9) are located within the recesses of the annular contacts, they will not be deformed. Since the film contacts (81) are prepared by etching and plating, the pitch can be easily narrowed, or otherwise modified.

Abstract: A semiconductor device (60) may comprise a semiconductor layer (12) having an outer surface (20). A plurality of gates (18) may be disposed over the outer surface (20) of the semiconductor layer (12). An isolation cover (30) may be disposed over the gates (18). An implant screen (40) may be grown on the outer surface (20) of the semiconductor layer (12) between the isolation covers (30) of the gates (18).

Abstract: A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.

Abstract: A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N- conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12).

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: A phase locked loop ("PLL") 28 containing apparatus for automatically causing the PLL to achieve phase lock when first energized or after having lost phase lock. In addition to a phase detector 4, loop filter 13, voltage controlled oscillator ("VCO") 14 and feedback from the VCO to the phase detector 16, the PLL has a sweep circuit 30. The sweep circuit cooperates with the loop filter when the PLL is not in phase lock to automatically generate a control voltage for the VCO which control voltage increases linearly with time until the PLL achieves phase lock or until the control voltage has reached the largest voltage in the dynamic input range of the VCO. In the event that phase lock is not achieved during the period of the increasing voltage, the control voltage decreases linearly with time to drive the PLL into phase lock.

Abstract: A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected.

Abstract: A novel Finite Impulse Response ("FIR") filter (10)" is provided with precise timing acquisition. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (34). A plurality of slave sample and hold circuits (36-44) are coupled to the output of the master sample and hold circuit. The outputs of the slave sample and hold circuits (36-44) are multiplexed to a plurality of multipliers (14-22) in a round robin manner.

Abstract: Active integrator optical sensor (13) having a photodetector (56) and an active integrator circuit. The active integrator circuit having an operational amplifier (50), an integrating capacitor (51) an offset capacitor (54) and a store capacitor (52). The active integrator circuit operating to integrate the electrical signal from photodetector (56).

Abstract: A plurality of substrate bias circuits (14, 16, and 18) are designed to provide a stable substrate reference potential for a variety of operating modes. Only one of the bias circuits is enabled by a control circuit (12) at any time for any operational mode. An on-demand boost bias circuit (16) is enabled whenever a level detector (20) indicates substrate bias has exceeded a predetermined limit during special operating modes such as burn-in or parallel test.

Abstract: A method of fabricating a bipolar transistor concurrently with an MOS device comprising the steps of forming an NPN bipolar transistor by providing a semiconductor wafer (1) having a semiconductor region (3) of predetermined conductivity type having a surface. An emitter region (33) and a collector contact region (35) are formed in and extend to the surface of the semiconductor region (3) of predetermined conductivity type with an implant of the predetermined conductivity type. An intrinsic base region (43) is formed extending to the surface by implanting an impurity of opposite conductivity type in the semiconductor region (3) isolating the emitter region (33) from the semiconductor region of predetermined conductivity type. An insulating layer (49) is formed on the semiconductor region of predetermined conductivity type extending over all transitions at the surface of the predetermined conductivity type to the opposite conductivity type.

Abstract: The invention provides improved architectures and methods for emulation, simulation, and testability of data processing devices and systems without requiring physical probing or special test fixtures. A data processing device may include a semiconductor chip that is divided into domains. One domain may be halted and tested while another domain continues to operate. For example, the semiconductor chip may have a electronic processor domain and an analysis domain. The analysis domain may include an on-chip condition sensor that is connected to the electronic processor domain. The chip can further include control logic circuitry to allow the analysis domain to operate while the electronic processor is halted and tested.

Abstract: An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element.

Abstract: A method of resolving the frequency ambiguities which result when the instantaneous bandwidth of a digital receiver exceeds the sampling frequency of the digital to analog converter. The frequency ambiguities which result from sampling an input signal below the Nyquist rate are resolved by simultaneously sampling the signal at multiple sample frequencies and then using a lookup table to identify the unique mapping of the common signal into the multiple sample frequency baselines.

Abstract: A pipelined analog-to-digital converter is disclosed having a plurality of sample and hold converter stages, each having an interstage amplifier (28) associated therewith. This is a differential amplifier that is implemented without common-mode feedback. The sample and hold stage operates on a reset phase and a gain/DAC phase, wherein the output of the reconstructive DAC is summed with the input to the amplifier (28). A differential input amplifier (60) has the inputs thereof set to common-mode input voltage with a feedback capacitor biased to a common-mode output bias point. During the gain/DAC phase, the bias input is removed and the feedback capacitor connected across the input/output of the amplifier (60). This effectively establishes the common-mode bias points for use by the amplifier (60) during the gain/DAC phase.