Abstract: Circuits, systems, and methods relating to operating a computer system operable in a system manager mode (24). The method includes various steps. The first step (34) occurs during operation of the computer system (10) at a time other than start-up, and receives user power management data from a user of the computer system. The second step (38) stores the user power management data in memory space (30) accessible by the system management mode. The third step (40) accesses the user power management data from the memory space. Finally, the fourth step (42) controls at least one peripheral (14, 16, 18, 20) of the computer system in response to the accessed user power management data.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. During emulation, the fetching of instructions from program memory can be halted.

Abstract: An error-correcting dynamic memory (100) which performs error correction (110) only during refresh or during the second (or subsequent) read of a burst read or during a writeback. Further, the memory may contain an error-correction-code-obsolete bit in addition to data bits and check bits in order to generate check bits during refresh and not during write. This provides error correction without read access delay or write delay at the cost of slightly more exposure to soft errors.

Abstract: In a method embodiment (10), the method operates a microprocessor (110), and the microprocessor has an instruction set. The method first (11) stores an identifier code uniquely identifying the particular microprocessor in a one-time programmable register. The method second (12) issues to the microprocessor an identifier request instruction from the instruction set. The method then, and in response to the identifier request instruction, provides (18) from the microprocessor an identifier code. Other circuits, systems, and methods are also disclosed and claimed.

Abstract: A method of fabricating a monolithic device, preferably a micromechanical device, from a wafer (20) by carefully selecting the composition of two or more layers of photoresist (52,54). The present invention uses a superhard protective layer such as DLC or TiW deposited over the partially fabricated device prior to a partial-saw. This superhard protective layer reduces the generation of defects in the underlying photoresist layers, and allows a wet chemical HF acid to etch away particles and damage of the underlying oxide edges. A 6% BHF solution can be utilized. The present invention substantially improves the yield of micromechanical devices.

Abstract: A method of fabricating an oxidation barrier for a thin film is provided. The method may include forming a thin film (10) outwardly from a semiconductor substrate (12) and separated from the semiconductor substrate (12) by a primary insulator layer (14). A reactive layer (16) may be formed in-situ adjacent to the thin film (10). An oxidation barrier (20) may be formed by a chemical reaction between the thin film (10) and the reactive layer (16). The oxidation barrier (20) may comprise a silicide alloy that operates to reduce oxidation of the thin film (10).

Abstract: A device and method of making the device for regulating electromagnetic radiations in a predetermined frequency range, which comprises a substrate and a coating mixture on a surface of the substrate. The coating mixture is provided by mixing together: (a) a plurality of flakes of a magnetic or ferrite material having substantial length and width dimensions relative to their thickness, the thickness of substantially all of the flakes being less than the skin depth of all frequencies in the predetermined frequency range, (b) at least one surfactant, (c)) a vaporizable electrically insulating material and (d) a solvent. The mixture is sprayed onto the surface of the substrate, either with or without a magnetic field at the surface, and the solvent is removed to retain the flakes on the substrate spaced from each other by the electrically insulating material and disposed substantially parallel to the portion of the plane of the surface thereunder.

Abstract: Video images are displayed from a sequence of frames or lines of video signals from a prerecorded source of frames or lines, respectively. A direction that a user is facing is determined by a directional device and a portion of the sequence of frames or lines are stored based on the direction determined by the directional device. The stored portion is read from memory and displayed for the user.

Abstract: A method of using a processor-based integrated circuit (IC) tester (12) to automatically invoke diagnostic testing. A diagnostic schedule (30) is user-defined (FIG. 3), and checked by the tester (12) at various times, such as before and after the tester 12 tests an IC lot (FIGS. 6, 7, 8). The schedule (30) has various scheduling parameters that permit diagnostic testing to be scheduled to occur at certain times, at the expiration of intervals, or upon certain events. The schedule (30) also permits different levels of diagnostic testing, each level with its own schedule. The tester (12) is programmed to run an appropriate level of diagnostic testing if more than one level is due to occur.

Abstract: An integrated circuit with an intermetal level dielectric (IMD) including an organic-silica hybrid (110) and located between metal lines (104).

Abstract: A capacitive transducer (10) which provides an output voltage in response to the application of a mechanical stimulus such as pressure or acceleration includes a signal conditioning integrated circuit (12) to which are connected a variable capacitor (C.sub.VAR), a reference capacitor (C.sub.REF), a linear correction capacitor (C.sub.LIN) as well as an integrating capacitor (C.sub.INT) and associated filtering components. The linear correction capacitor (C.sub.LIN) is used to offset a fixed parasitic charge associated with the variable capacitor. Any net error charge appearing on a detect, common node (pin 4) between the variable capacitor and the reference capacitor is cancelled out by means of an analog feedback network (22). In a modified embodiment a thermal compensation network (40) allows for correction for thermal error at a second temperature without having any affect at a first temperature.

Abstract: The invention is to a mounting device (12) and to a method of mounting a semiconductor die (11) to a mounting surface (10) to ensure that the die (11) is in a plane parallel to the mounting surface (10). An intermediate woven mounting device (12) having two parallel faces and having a plurality of co-planer mounting points (13a and 14a) on each of the parallel faces is placed on a semiconductor mounting surface (10) and the semiconductor die (11) is placed on the intermediate device. Along with a die attach adhesive, heat and pressure is applied to secure the semiconductor die (11) and intermediate mounting device (12) to the mounting surface (10).

Abstract: A VLIW microprocessor capable of executing two or more instructions having data dependency in a single cycle. The microprocessor includes an instruction fetch and decode unit, a register file, and a plurality of execution units communicating with the instruction fetch and decode unit and with the register file. At least two of the execution units are connected such that the output of a first one of the two execution units is connected to the input of a second one of the two execution units, such that the output of the first execution unit is available as an input to the second execution unit during said single cycle, and such that both execution units can execute in said single cycle. In an exemplary embodiment, the first execution unit is a shift left unit, and the second execution unit is a shift right unit. With this embodiment, a complete extract operation can be performed in a single cycle.

Abstract: A method of increasing the brightness of a pulse width modulation display system. Image bits are displayed during display periods having a non-binary relationship. The display period of an object bit 902 is set equal to a minimum data load time, and the display periods of all other bits are initially set to have a binary relationship with the object bit. The display periods of at least one non-object bit 904, 906, 908 are then reduced in order to reduce the total frame time to no more than the available useable frame time 910. Preferably, only the display periods of bit of significance greater than the object bit are reduced. The reduction of display periods is guided by Weber's law, in order to prevent the non-binary steps from being noticeable or objectionable to the viewer.

Abstract: A flow regulating valve (100) for an air conditioning system is shown in which a body member (104) is provided with a fixed passageway (104a) and a variable passageway (104b) which results in regulating flow of refrigerant into the evaporator of the air conditioning system. Under high ambient and low or idle speeds, the system refrigerant pressure rises. This increases pressure in the evaporator and an increase in the saturation temperature of refrigerant in the evaporator. This increase in temperature is sensed by a helical thermostatic metal element (110) which moves to rotate an inlet sleeve (112) having a web (104c) formed between first and second windows (112a, 112b) to move into alignment with the inlet port (104c) of passageway (104b) to increase restriction to the flow of the refrigerant fluid through the valve thereby decreasing pressure of the refrigerant entering the evaporator.

Abstract: The present invention is a method and system which determine signal probability and transfer probability for each node in a netlist describing an electrical circuit; determine, using the signal probability and transfer probability, a fault detection probability for each node; and, using the fault detection probabilities, determine overall fault coverage of the electrical circuit described in the netlist. The method and system of the present invention then, using the fault coverage data, heuristically determine a set of testpoints to be inserted into the netlist which increase the overall fault coverage of the electrical circuit above a predetermined value.

Abstract: A semiconductor device (10) of the present invention has a gate (32) insulatively disposed above the substrate, source and drain regions (36, 38) disposed near the surface in the substrate adjacent opposite sides of the gate (32), and a field oxide region (26) disposed in the surface of the substrate surrounding the source and drain regions (36, 38) and defining an active moat region (20). The channel stop region (24) is disposed below the field oxide region (26) and is spaced from the active moat region (20) with a predetermined spacing.

Abstract: A system for providing feedback to a selected read head in a multi-head disk drive includes first and second feedback circuits is disclosed. A first feedback circuit 200 provides for correction of the output of the selected read head during normal operation. The first feedback circuit 200 produces a differential output current proportional to an offset voltage detected on the read head output nodes 103 and 104. This differential output current charges external capacitor 190. The voltage across capacitor 190 is supplied to voltage inputs of the selected read head as a feedback voltage. When the feedback voltage reaches the desired level, nodes 103 and is 104 equalize, as do the output currents of the first feedback circuit 200. The second feedback circuit 300 provides for quick recovery of the system after a change in read heads.

Abstract: A computer system includes a mobile electronic device (30) which can be coupled to a network (18) either directly or through a receiving station (32) such as a docking station or a port replicator. A splitter module (36) is coupled to network connectors (14a and 14b) on both the mobile electronic device (30) and on the receiving station (32) to communicate with either network connector (14a or 14b).

Abstract: A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store data in a first register into memory if a selected status bit has a first state and to store data in a second register associated with the first register into memory if the selected status bit has a second state in response to a register pair conditional store instruction. The bits may indicate a negative output of the arithmetic logic unit (230), a carry out signal, an overflow, or a zero output. The register pair conditional store instruction designates a particular one of the status bits to control the conditional store. The instruction logic circuit (250, 660) substitutes the selected status bit for a least significant bit of the register number. Thus memory store is from the first register if the status bit is "1" and is from the second register if the status bit is "0".