Abstract: A burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-in process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ, and lowering the temperature of the memory array to ambient temperature to complete the burn-in process. An apparatus for carrying out the above process is provided that includes a test circuit for generating a test pattern and for applying the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response and an expected response of the memory array to the test pattern and detects faulty and operable bits based thereon.

Abstract: A method and circuit for comparing the frequencies of two clocks (clock—1 and clock—2), without taking into account their phase, is disclosed. Each clock is associated to a circular counter (100-1 and 100-2) which are initialized to different values, and the contents of the circular counters are compared. When the frequencies of the two clocks (clock—1 and clock—2) are equal, both counters (100-1 and 100-2) are incremented at a common frequency and thus, due to the initialization conditions, the contents of both counters can never be equal. Conversely, when the frequencies of the two clocks are different, the counters (100-1 and 100-2) are not increased at a common frequency and thus, after several clock pulses, the contents of the counters are equal, indicating different clock frequencies. In a preferred embodiment, the circular counters (100-1 and 100-2) are 2-bit circular counters.

Abstract: The operating lifetime of a hot cathode discharge ion source is extended by introducing nitrogen into an ion implantation apparatus after introduction of an ion implantation gas, such as GeF4, is stopped. The nitrogen is preferably introduced along with the GeF4 during implantation as well.

Abstract: A method for determining common failure modes of an integrated circuit device under test is disclosed. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs of the device under test. A set of output data generated by the device under test is then compared to a set of expected data, with the set of output data being generated by the device under test in response to the test pattern. It is then determined whether the set of output data has passed the test, with the set of output data passing the test if the set of output data matches the set of expected data. If the set of output data has not passed the test, then it is determined whether an output signature corresponding to the set of output data matches a previously stored output signature. Fail data corresponding to the output signature is then stored if the output signature matches a previously stored output signature.

Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.

Abstract: A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area.

Abstract: An integrated test structure adapted to facilitate manufacturing verification of microelectronic devices such as Digital to Analog Converters (DAC) is disclosed. The test circuitry and the Circuit Under Test (CUT) are placed on an IC along with an arbitrary amount of digital logic, which drives the input of the CUT. These inputs are translated into an analog output. During a manufacturing test, this output is measured in order to determine that the IC has been manufactured correctly. The analog input of the circuit is coupled to the analog output of the DAC. The digital output of the test circuitry is coupled to the digital logic on the IC. This configuration comprises a Built In Self Test (BIST) structure. The invention allows BIST by eliminating the need to measure the analog output of the DAC external to the IC, and enables testing the CUT by using standard digital BIST techniques.

Abstract: An SRAM which eliminates any seam in consecutive read/write data flows when the burst-length is short, thus making it possible to achieve a seamless access in the burst-mode against data of different row-addresses between banks. This operation enables the band-width of SDRAM to approximate the data transmission rate at the peak moment determined by the maximum frequency of the clock.

Abstract: A driver circuit and receiver circuit to reduce power consumption of a digital signal transfer circuit is described. A driver circuit 20 includes a PFET 21, an NFET 23, and an NFET 22 having a low threshold voltage. An input signal DIN-bar is supplied to a gate of the PFET 21, and a reference voltage Vref is supplied to a gate of the NFET 22. A signal having a small amplitude restricted by Vref is outputted from the driver output DOUT. A receiver circuit 40 having a PFET 41 and NFETs 42 and 43 having low threshold voltages, and an inverter having a PFET 44 and a NOT gate 45. The receiver circuit 40 shifts the level of the signal with the small amplitude, drives it with the inverter and outputs a signal ROUT having a CMOS level.

Abstract: It is one object of the present invention to eliminate redundant testing steps from an operation for testing the search function of a content addressable memory having a priority encoder. Before testing is conducted, background data that differ from test data are written (step 21). Then, the background data are read (step 22) and are tested (step 23). The address having the lowest priority is designated (step 26). And the test data are written thereto (step 27). Following this, the search operation is performed (step 28) to determine whether test addresses match search addresses (step 29). Then, the address having the second lowest priority is designated (step 26), and the above processing is repeated for all the addresses (step 32).

Abstract: A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.

Abstract: This is a circuit and protocol for relaxing the strobe to data relationship to permit the writing into and reading out of a double data rate DRAM array at data transfer rates higher than any known circuits that utilize a strobe and data protocol. This result is accomplished by modifying the prior art write circuitry by adding a strobe generator coupled to both the data input and the strobe input to control the write circuit multi-latch and by modifying the prior art read circuit by coupling the initial and enable circuit to the data drivers and adding a data compare circuit that is coupled between the memory storage array and the strobe toggle to control the strobe. In this way the present invention relaxes the use of the strobe to data relationships for reads and writes except when there are no data transitions and ends the necessity of aligning the strobe with the data eye.

Abstract: A memory cell system for a dynamic random access memory (DRAM) array is disclosed. In an exemplary embodiment of the invention, the system includes a plurality of data storage elements arranged in rows and columns. A plurality of wordlines corresponds to the columns, and a plurality of lower bit lines corresponds to the rows, with each of the plurality of lower bitlines further being associated with a plurality of upper, complementary bitlines thereto. The plurality of upper bitlines are vertically aligned with the plurality of lower bitlines, thereby defining a plurality of vertically folded bitline pairs. Further, a plurality of sense amplifiers are arranged in the rows, with each of said plurality of sense amplifiers having one of said plurality of vertically folded bitline pairs as inputs thereto. When one of the plurality of wordlines is activated, a subset of the rows corresponding to the vertically folded bitline pairs is activated.

Abstract: Method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effetively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices.

Abstract: A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gated by a combinatorial logic gate. Each sub-entry's structure is that of a short CAM entry with a short Match Line (a match line segment) with a small capacitance. Each CAM block outputs a signal that can enable or inhibit a CAM search in the sub-entry in the next CAM block. A variety of exemplary circuits for gating match line segments within CAM blocks, and methods of selecting and combining the resulting variety of CAM blocks to obtain power-savings and/or high performance. An ASIC library including library elements having electrical rules that describe devices within and describe interconnections between the devices within a CAM block.

Abstract: A dynamic random access memory includes first and second address generators, subarrays, an address decode path and a precharge activation path, wherein the precharge activation path and the address decode path are matched. The first address generator identifies a word and a column address. The second address generator identifies a subarray address. The subarrays include a number of cells for storing data. The address decode is configured to transmit address and other information while the precharge activation path is configured to transmit a precharge activation signal. In a preferred embodiment, an event during an active phase process, such as a sense amplifier set signal initiation, initiates the precharge phase process.

Abstract: An oxidation exhaust trap for filtering a particulate product of a first gas contacted with a gaseous oxidizing agent. The oxidation exhaust trap has a vessel having an interior cavity. The vessel further having a first inlet in communication with the interior cavity for introduction of the first gas into the interior cavity and a second inlet in communication with the interior cavity for introduction of the gaseous oxidizing agent into the interior cavity, the gaseous oxidizing agent mixing with the first gas thereby causing oxidation of the first gas for producing the particulate product suspended in a gaseous product. Lastly, the vessel has an outlet in communication with the interior cavity. A filter is disposed in the interior cavity for filtering the particulate product from the gaseous product which is exhausted through the outlet. In a preferred embodiment of the present invention, the first gas is silane and the gaseous oxidizing agent is air.

Abstract: Disclosed is a programmable impedance driver that includes two sets of impedance devices, two primary counters and two test counters. The primary counters selectively activate individual ones of the impedance devices to vary an overall impedance of the driver and the test counters verify the counting operation of the primary counters during manufacturing testing of the driver. Therefore, the built-in self-test (BIST) aspect of the invention easily detects if one of the counters will become stuck during normal usage.

Abstract: A method for configuring a bypass capacitor for use in conjunction with an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes selecting mechanical dimensions for the bypass capacitor, the mechanical dimensions causing the bypass capacitor to exhibit electrical losses at a clock frequency of the integrated circuit device. The bypass capacitor preferably includes a ferroelectric dielectric material. In addition, the selection of mechanical dimensions for the bypass capacitor determines a mechanical resonance frequency for the bypass capacitor, with the mechanical resonance frequency corresponding to the clock frequency.

Abstract: A socket for testing or burning-in electronic components has a cover including a heat sink and a sensor. The heat sink and sensor are spring loaded so they make direct, temporary contact to an electronic component in the socket during burn-in. A heat transferring device is coupled to each heat sink. The heat transferring device uses input from the sensor to provide heat or cooling to each heat sink to individually control the temperature of each component. The heat transferring device can be an electric heater or a cooling device, such as a fan. Both can also be used. A plurality of these sockets are used in a forced air convective oven for burning-in a plurality of electronic components at one time. The oven provides oven heating and cooling for all components while the socket heater and sensor provide individual temperature control for each component.