Abstract: A liquid crystal display and manufacturing method therefor. The liquid crystal display includes two opposing electrodes, a plurality of electric-field-effect liquid crystal layers disposed between the two electrodes, insulating layers for dividing the liquid crystal layers, main supports for maintaining a predetermined distance between the insulating layers, and auxiliary supports provided about liquid crystal injection holes through the insulating layers, the auxiliary supports preventing the deformation of the liquid crystal injection holes and facilitating the injection of liquid crystal.

Abstract: The plasma display panel comprises two substrates onto which parallel cathodes and anodes are attached, respectively. When the anode and cathode substrates are connected together by barriers, which also prevent the cross-talk between pixels, the cathodes and anodes are perpendicular to each other. The cathodes are made of thin metallic wires that attach to the rear substrate. Fabricating the cathode structure comprises the steps of: preparing a compound fiber in which a plurality of metallic lines are arranged in parallel and a plurality of thermoplastic threads are arranged perpendicular to the metallic lines; placing the compound fiber on the rear substrate; and baking this combination.

Abstract: Disclosed is a dynamic random access memory device (DRAM) having an increased cell capacitance and simplified manufacturing method thereof. The storage electrode the capacitor of the DRAM is connected to a semiconductor substrate through an opening formed in an insulating layer, and has a structure having an outer peripheral wall portion with a laterally extending bottom on the insulating layer and an inner central pillar portion including a hole of a certain depth within the opening in the center of the outer peripheral wall portion. Thus, cell capacitance is greatly increased within a limited unit cell area, its reliability is enhanced, and the manufacturing process is distinctly simplified.

Abstract: An error correction system including a syndrome modifier for receiving a syndrome and operating the equation ##EQU1## where i is an integer greater than or equal to zero, for transforming the syndrome into a new syndrome; an n-1 error correction circuit for receiving the syndromes modified by the syndrome modifier for n-1 error correction, a counter for varying the K value if the n-1 error correction fails; a circuit for outputting an .alpha..sup.K value corresponding to the K output signal of the counter, to the syndrome modifier, an error value operation circuit for receiving the output signal of the n-1 error correction circuit to calculate a substantial error value according to the equatione.sub.i =e'.sub.i /(1+.alpha..sup.i-k)where i is an integer greater than or equal to zero; and an adder for receiving and adding the output signal and the syndrome from the error value operation circuit, to perform a final error correction.

Abstract: A method for correcting multiple erroneous symbols included in data produces a demodulation flag indicating whether demodulation based on a modulation code such as EFM or ETM is possible. The demodulation flag is used in decoding the data based on the error correcting code. Producing the error locations during decoding in accordance with a Reed-Solomon code comprises the steps of producing an index using ##EQU1## provided .sigma..sub.1, .sigma..sub.2 and .sigma..sub.3 represent coefficients of an error location polynomial, k.sub.1 represents .sigma..sub.1.sup.2 +.sigma..sub.2 and k.sub.2 represents .sigma..sub.1 .sigma..sub.2 +.sigma..sub.3, reading out virtual roots from a specified memory related to the index, and transforming the virtual roots (Z.sub.1, Z.sub.2 and Z.sub.3) into error locations (x.sup.j1, x.sup.j2 and x.sup.j3) in accordance with the following equations.x.sup.j1 =Z.sub.1 (k.sub.1)+.sigma..sub.1x.sup.j2 =Z.sub.2 (k.sub.1)+.sigma..sub.1x.sup.j3 =Z.sub.3 (k.sub.1)+.sigma..sub.

Abstract: An electrically erasable programmable read only memory (EEPROM), having error checking and correction circuitry uses a separation circuit to electrically isolate a temporary page buffer memory from a memory array so that better reliability of parity generation and error correction is provided. The EEPROM memory array includes a plurality of bit lines, a plurality of memory cells respectively connected to the bit lines and parity cells. The error check and correction circuit includes a column gate logic, connected to the plurality of bit lines, for temporarily loading randomly input data onto a memory page buffer. The EEPROM processes the data in the page buffer to logically store it as multi-byte data, simultaneously together with appropriate parity bit data corresponding to each multi-byte data set, in the memory array.

Abstract: A storage electrode of a capacitor of a semiconductor memory device and a method for manufacturing the same are disclosed. A first electrode of the capacitor comprises a main electrode having a plurality of microtrenches and micropillars formed therein, an outer wall surrounding the microtrenches and micropillars, a granular silicon layer formed on an outer sidewall of the outer wall, and a column electrode supporting the main electrode and electrically connecting the main electrode to a source region of a transistor of the semiconductor device. The first electrode preferably has a horizontally fin-structured auxiliary electrode formed underneath the main electrode and electrically connected to the column electrode of the first electrode. The capacitor may be formed by using an etching end-point detection layer and an HSG polysilicon layer. The effective surface area of the storage electrode of a capacitor is increased to thereby obtain adequate cell capacitance.

Abstract: In a method for forming an isolation region in a semiconductor device, after forming a first oxide film and a silicon film on a semiconductor substrate, an oxidation-blocking film is formed on the silicon film. Then, a high-temperature heat treatment process is performed in a nitrogenous atmosphere. The oxidation-blocking film is selectively etched to form an opening, and a thermal oxidation process is performed to form a thermal oxide film in the opening. A bird's beak between the oxidation-blocking film and the silicon film is suppressed because of the heat treatment in a nitrogenous atmosphere, so that stable isolation characteristics can be secured.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device. A conductive layer is formed on the semiconductor substrate and a photoresist pattern is formed on the conductive layer. The conductive layer is etched, using the photoresist pattern as a mask to form a first step-portion in the conductive layer. A first spacer is formed on a sidewall of the photoresist pattern, which may be formed by flowing the photoresist pattern. The conductive layer is etched, using the first spacer as a mask, to form a second step-portion in the conductive layer. The photoresist pattern and the first spacer is removed. A first material layer is formed on the entire surface of the resultant structure and etched to form a second spacer on the sidewalls of the first and second step-portions. The conductive layer is etched, using the second spacer as a mask, to form a storage electrode of a capacitor. Cell capacitance may be increased by a simple process, and the heat cycle may be reduced.

Abstract: A method for forming contact holes having different depths in an insulating layer which covers a semiconductor substrate. A first step selectively etches the upper parts of the insulating layer which correspond to contact holes having a greater depth than the shallowest contact hole, using a first mask pattern. A second etch step selectively etches the remainder of the insulating layer for all of the contact holes at the same time using a second mask pattern. Thus, contact hole misalignment is kept to a minimum.

Abstract: The present invention forms a intermediate layer between a conductive layer and BPSG layer. In one embodiment, this intermediate layer is a buffer layer that absorbs excess P ions from the BPSG layer to suppress the formation of bubbles and thereby prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer. In the second embodiment the intermediate layer is a thin nitride layer, which prevents the conductive layer and BPSG layer from being in direct contact with each other to suppress the formation of bubbles and also prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer.

Abstract: A semiconductor memory device includes a plurality of memory cells each having a single transistor and a single capacitor on a semiconductor substrate. The capacitor has a storage electrode with an externally communicated box-type tunnel in its center, one portion of the storage electrode being connected to the source region of the transistor. A method for manufacturing the semiconductor memory device is also provided. Thus, storage capacity is raised by increasing the effective area of the capacitor, and the planarizing effect is also excellent.

Abstract: A semiconductor SRAM device is provided wherein the electrical characteristics of the memory cell of the SRAM device is enhanced by decreasing the OFF-current and by increasing ON-current of PMOS thin film transistor (TFT) load elements. An offset region is formed between the drain and channel regions of the PMOS TFT. The gate is formed below (or above) the channel region of the PMOS TFT, and an insulating layer is formed below the gate. A ground potential V.sub.ss conductive layer is formed below the insulating layer, facing the offset region, to thereby operate as a gate for the offset region. The ground potential of the conductive layer facing the offset region of the PMOS TFT is constantly ON because of the gate operation of the ground potential conductive layer. A higher ON/OFF current ratio results, and the electric characteristics of the PMOS TFT load elements and therefore the SRAM device are thereby enhanced.

Abstract: A capacitor of a semiconductor memory device having a greater cell capacitance than a double-cylindrical capacitor and an improved method for manufacturing the same are disclosed. A first conductive layer is formed on a semiconductor substrate and then first and second material layers are formed on the first conductive layer. The first material and second material layers are patterned to form a composite pattern comprised of a precursory first material pattern and a second material pattern. The precursory first material pattern is anisotropically etched to form a first material pattern smaller than the second material pattern. Here, an undercut portion under the second material pattern is created. Then, the first conductive layer is anisotropically and partially etched to form a first conductive layer pattern having a groove defining a protruding stepped portion into an individual cell unit.

Abstract: An SRAM memory cell structure is provided which has the access transistor gates formed from a different layer than that of the word line. The first access transistor gate of a first memory cell is connected to the first access transistor gate of an adjacent second memory cell, and a second access transistor gate of the first memory cell is connected to a second access transistor gate of an third oppositely adjacent memory cell. Each pair of coupled gates are formed separate from the access transistor gates in adjacent memory cells. The word lines connect the separated access transistor gates. The word lines are formed on an insulating layer above the gates of the access transistors. The word lines are, however, electrically connected to the gates of the access transistors through contact holes formed in the insulating layer. Each memory cell is arranged symmetrically with respect to an adjacent memory cell, and the components of each memory cell are symmetrical.

Abstract: A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.

Abstract: A charge-coupled device (CCD) is provided having improved charge transfer efficiency. This CCD is a portion of an image sensor and manufactured by first laminating a first oxidation film and a first nitride film one after the other on a semiconductor substrate and then forming a plurality of first gate electrodes on the first nitride film at predetermined intervals apart. A second oxidation film is formed only on an upper surface and along side walls of each of the first gate electrodes. The first nitride film exposed between the first gate electrodes is removed and a second nitride film is formed on the exposed first oxidation film and the second oxidation film. A second gate electrode is then formed on the second nitride film between adjacent first gate electrodes. An image sensor is obtained in which leakage current density between the gate electrodes is reduced and the dielectric characteristic of a gate dielectric film is improved.

Abstract: An LOC type semiconductor package and a fabricating method thereof comprises first and second through holes formed at inner leads and bus bars of the LOC-type lead frame, and third through holes formed at the tape which is bonded with the lower side of the inner leads and the bus bars, by pins at a tape cutter. Thus, air existing at both tape during the bonding process effectively flows out so as to prevent the trapping of air bubbles. Accordingly, during the wire bonding process, wire shorting and damage to the package body can be prevented. Since EMC is deposited into the first and the second through holes and supports the inner leads and the bus bars during the molding of the semiconductor package, the reliability of the semiconductor package can be improved.

Abstract: A circuit is provided for protecting the internal circuit of a semiconductor device from electrostatic discharge (ESD). This circuit includes an input pad for applying an input signal to the internal circuit, a metal line for electrically connecting the input pad and internal circuit. This metal line has at least one RC delay stage caused by inherent parasitic resistances and capacitances. Also, a punch-through element is provided to connect the metal line to a ground voltage terminal disposed between the input pad and a delay stage. Finally, a resistor is used to connect the at least one delay stage to the internal circuit.

Abstract: A method for forming a mask pattern using a multi-layer photoresist film process is disclosed. The processing is simplified from known processes by using a silylated photoresist film. A first photoresist layer is formed on substrate and part of the surface of the photoresist layer is silylated to thereby form a silylation layer. Then, a second photoresist layer is formed on the silylation layer, which is then exposed through the photo mask having a predetermined pattern. A second photoresist pattern is then formed after development. Then, a silylation layer pattern is formed by etching-back the silylation layer using the second photoresist pattern as an etching mask. The silylation pattern is then oxidized, and the first photoresist layer is etched using the oxidized silylation pattern, thereby forming a first photoresist pattern. A resolution increasing effect can be maintained using the two layer photoresist film structure without the need for an intermediate oxide film.