Abstract: A manufacturing method for a semiconductor memory device including a capacitor having a double fin-shaped structure is provided, wherein a storage electrode is formed by applying a thick planar material capable of being wet-etched between the double fins consisting of conductive layers. The storage electrode is formed by forming a thin, high temperature oxide film having an etching rate which is great. Thus, the resulting memory cell's topography is improved and damage to the storage electrode is decreased.

Abstract: A method of obtaining a multi-level liquid crystal device repeatedly applies a metal layer and then oxidizes a portion of that metal layer. Thereafter, the non-oxidized layers are removed, leaving empty layered spaces into which liquid crystal can be filled.

Abstract: A manufacturing method for a thin film resistor is disclosed. An insulating layer is formed on a substrate having a contact region. The insulating layer above the contact region is removed by etching to expose the contact region. A metal layer and an interlayer are then formed in sequence on the surface of the structure. The metal layer and the interlayer above the region where the resistor will be formed is next removed, and then a resistor layer is formed on the surface of the structure. The thin film resistor is completed by etching away the resistor layer except for the predetermined region where the resistor is to be formed.

Abstract: A method for forming a pattern improves a profile of a resist pattern. The method forms a photoresist layer on a substrate having a step, and exposes the photoresist layer using a first mask. Then, thick portions of the photoresist layer are exposed using a second mask, and the entire resist is developed. The second mask provides an additional increment of energy to thick regions so that no inadequately exposed resist material will remain near the step.

Abstract: A compound semiconductor device is disclosed which comprises a crystally grown buffer layer formed on a semi-insulating semiconductor substrate provided with an insulating layer. The crystal growth characteristics are such that the insulating layer does not allow crystal growth on its upper surface. During its growth, the buffer layer makes reverse sloped side edges which join to form a void. A gate electrode formed above the void separates a channel from the substrate. In the .delta.-MESFET, side walls are formed at both sides of the gate electrodes and an N.sup.+ -well region is formed by using the side walls as an ion implanting mask. Accordingly, the void separates the channel from the semiconductor substrate, thereby preventing leakage current through the buffer layer, backgating effects in an integrated circuit, and completing crystal growth without an undue effort for lowering the impurity concentration of the buffer layer.

Abstract: A low-frequency oscillator whose duty ratio can be simply controlled includes a charging and discharging circuit for charging a capacitor via a constant current source and then discharging the capacitor according to a discharge control signal. A voltage comparator compares the voltage across the capacitor with a reference voltage. A monostable multivibrator, triggered by the output of the voltage comparator, generates the discharge control signal. The duration of the discharge is determined according to the RC time constant of the monostable multivibrator, to thereby generate a rectangular waveform having an accurately controlled duty ratio.

Abstract: A data output buffer of a semiconductor integrated circuit is operable in response to data input to data lines and comprises a first pull-down control circuit which generates a first pull-down signal in response to the data input to the data lines. A second pull-down control circuit generates a second pull-down signal in response to the data input to the data lines, the second pull-down signal being generated at a predetermined time after the first pull-down signal is generated and causing the first pull down signal to be deactivated. A first pull-down transistor shares an output node with a pull-up transistor and is responsive to the first pull-down signal to pull-down a predetermined amount of voltage at the output node. A second pull-down transistor is responsive to the second pull down signal for pulling down a residual amount of voltage at the output node.

Abstract: The present invention relates to a static random access memory device, which has a precharge circuit for precharging bit lines to a predetermined voltage level in response to a precharge signal, a memory cell connected to a word line and bit lines for storing data, a word line selection address generating device for selecting the word line, a bit line selection address generating device for selecting the bit line, a read control circuit having a shaping circuit controlled by a read enable signal for shaping a level of the data, a latch device for latching the data of the bit line to keep a predetermined logic threshold voltage corresponding to the shaping means, and a write control circuit connected to the bit lines for supplying data to the memory cell. The latch device is provided in the read control circuit and includes NOR gates whose output signals are crossly applied. Each of the NOR gates receives data having the first logic state and data having the second logic state.

Abstract: In a noise canceler, a pilot-canceling signal without noise is applied to the inverting input of a subtracter via a first MOS transistor. When a noise signal is present, a pilot signal and noise signal passing through a capacitor are applied to the inverting input port of the subtracter via a second MOS transistor to cancel the noise signal contained in the composite input signal. In the canceler, external noise may be digitally converted and the inverted noise thereof stored in a memory. When a noise signal detector detects the external noise, inverted data corresponding to the external noise is output from the memory. The detector enables an address generator to continuously generate addresses. The memory reads out inverted noise patterns which are converted into analog form and transmitted via a speaker, thereby canceling noises produced by various electrical and electronic appliances as well as nearby automobiles and aircraft.

Abstract: An improved static random access memory device of the CMOS load memory cell type for storing one-bit information is capable of 4M bit or greater memory capacity. Each memory cell includes two transfer transistors, two driving transistors, and two load transistor elements. Each load transistor element is a PMOS thin film transistor and comprises a source formed of first and second conductive layers and connected to a constant power source line, and a drain also formed of the first and second conductive layers and connected to the drain of a corresponding one of the driving transistors. A channel region of each load transistor element is composed only along the region defined by the second conductive layer and a respective gate is formed of a third conductive layer which is separated from the channel region by a gate insulating layer.

Abstract: A manufacturing method for a thin film resistor is disclosed. An insulating layer is formed on a substrate having a contact region. The insulating layer above the contact region is removed by etching to expose the contact region. A metal layer and an interlayer are then formed in sequence on the surface of the structure. The metal layer and the interlayer above the region where the resistor will be formed is next removed, and then a resistor layer is formed on the surface of the structure. The thin film resistor is completed by etching away the resistor layer except for the predetermined region where the resistor is to be formed.

Abstract: A word line boosting circuit and a control circuit therefor in a semiconductor integrated circuit are included. A word line boosting control circuit is connected to receive block select information selecting a first or second memory cell array block synchronized to a predetermined row address, and selectively generates first and second word line voltages.

Abstract: A method for manufacturing a double-cylindrical storage electrode of a capacitor of a semiconductor memory device, utilizes an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder. After forming a conductive structure on a semiconductor substrate, an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder are formed on the conductive structure. Then, the conductive structure is anisotropically etched using the outer and inner etching masks, thereby forming a double-cylindrical first electrode. Since a double-cylindrical storage electrode can be obtained from a single conductive layer, the influence of native oxidation circumvented. In addition, the double-cylindrical storage electrode of the capacitor according to the present invention decreases the risk of structural fragmenting because the electrode is obtained from one material layer, instead of a combination of layers as is conventionally-known.

Abstract: A volume/balance control apparatus includes a plurality of resistance arrays which correspond to a plurality of channels, a volume operator and a balance operator which generate volume and balance signals according to user's operation, an operation signal synthesizing means for producing synthesized control signals pertinent to each channel by synthesizing the volume signal and balance signal, and a plurality of decoders for decoding the output from the operation signal synthesizing means and applying the result to a switching element included in each resistance array. The volume/balance control apparatus has only one resistance array per channel, thereby improving noise characteristics, and permits the independent operation of volume and balance controls, thereby enhancing user convenience.

Abstract: A semiconductor memory device includes two latch circuits, each for holding data corresponding to a single normal address. When sequentially used, one after the other, one latch circuit can be storing new data while the other latch circuit outputs its data to the page decoder for subsequent output. Thus, data access delay times for page mode operation are further reduced because the delay which typically results from addressing a normal address is eliminated.

Abstract: A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.

Abstract: The present invention relates to an improved method of manufacturing pads of a display panel. Al or Al alloy is deposited and patterned on a glass substrate for forming a plurality of gate electrodes and lines. Then a plurality of pads are formed with Ta or Ti, which is capable of forming an anodic oxide thereof; each pad extending over an edge of each of the respective gate lines to provide an electrical coupling therebetween. Thereafter, the entire surface of the pads, gate electrodes and lines is subjected to an anodic oxidation under a high anodization voltage. Anodic oxide layers on the pads are then etched away together with a silicon nitride layer during a subsequent pad opening processing step. Consequently, in accordance with the invention, a photoresist masking process for the selective anodic oxidation of Al gate lines and electrodes is eliminated.

Abstract: In a semiconductor memory device, and in particular in a NAND-type ROM memory cell, the transistors of a memory cell region and a peripheral circuit portion are manufactured to include a first and second impurity regions. The second impurity region has a higher impurity density impurity than the first impurity region. A third impurity region is added which has a higher impurity density and shallower depth than the impurity density of the first impurity region. Accordingly, the conventional transistor structure of the peripheral circuit portion is maintained while the transistors of the memory cell are optimized to have ideal electrical characteristics, including an increased current driving capability.

Abstract: A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.