Abstract: Several embodiments of a computer system are described which achieve separation of control and data paths during data transfer operations, thus allowing independent scalability of storage system performance factors (e.g., storage system ops and data transfer rate). In one embodiment, the computer system includes a data switch coupled between a host computer and one or more storage devices. A storage controller for managing the storage of data within the one or more storage devices is coupled to the switch. The switch includes a memory for storing data routing information generated by the controller, and uses the data routing information to route data directly between the host computer and the one or more storage devices such that the data does not pass through the storage controller. Within the computer system, information may be conveyed between the host computer, the switch, the one or more storage devices, and the storage controller according to a two party protocol such as the Fibre Channel protocol.

Abstract: A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units.

Abstract: An apparatus for receiving an asynchronous data signal may include a clock generator that generates a clock signal having a frequency approximately equal to the bit rate of the asynchronous data signal. An edge detector may detect transitions of the asynchronous data signal. A dead-band detector may detect when a transition of the clock signal used to sample the data signal occurs within a predetermined amount of time of a transition of the asynchronous data signal so that data sampled on that transition of the clock signal may be invalid. The phase of the clock signal may be adjusted if the transition of the clock signal occurs within this predetermined amount of time.

Abstract: An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa.

Abstract: An apparatus and method are presented for monitoring the performance of a microprocessor. The apparatus includes performance monitoring hardware incorporated within the microprocessor. The performance monitoring hardware includes a memory unit for storing performance data. The memory unit includes multiple memory locations, each memory location being accessed by a unique set of address signals. Circuitry within the performance monitoring hardware produces the address signals. In one embodiment, the performance monitoring hardware includes an event select register array and circuitry for producing a set of high order (i.e., most significant) address signals. The event select register array preferably includes several event select registers for storing binary codes corresponding to selected events. A performance data acquisition period is divided into multiple histogram time periods of equal length. The high order address signals partition the memory unit into sections.

Abstract: A scalable performance storage architecture. The input/output operations per second (iops) and the data transfer rate are two very important performance measures of a storage system. Command and status information require little bandwidth, whereas data transfer is limited by the bandwidth of the storage controller busses, memory, etc. This invention first organizes the storage controller architecture into its functional units. The data paths that connect various functional units (for example, switching unit, parity logic, memory module, etc.) may then be sized to the required bandwidth. This effectively makes the iops and bandwidth capability of a storage controller scalable independently of each other, resulting in a selectively scalable storage system architecture. The system designer may increase the number of CPU's in a storage controller (for more iops) or the data bandwidth (for high aggregate data transfer rate) independently of each other.

Abstract: A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced.

Abstract: Disclosed is a system and method for providing a remote user with a virtual presence to an office. The method allows a user operating a remote computer system to receive a fax on a first communication line while simultaneously performing voice communications on the first communication line. The first communication line has an associated first telephone number. The remote computer system includes a user telephony communication device coupled to the first communication line. The method includes establishing a connection between the user telephony communication device and a virtual presence server. The user telephony communication device connects through the first communication line to the virtual presence server. The virtual presence server is located remotely from the user telephone communication device. A fax transmission is made to a second telephone number. The fax transmission is forwarded to the virtual presence server.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: A system and method for enabling a subscriber to receive incoming telephone calls on a telephone line and ring all of the telephones connected to a first conductor pair inside the subscriber's premises, wherein the first conductor pair would have normally been connected to the line. The telephones may be rung even when the subscriber is performing data communications with a remote data site on the telephone line. This obviates the necessity of the subscriber having to purchase a second telephone line for incoming calls while data communications are being performed, thus reducing access costs. The system and method shown advantageously employs a wiring device to reroute the telephone line from the first conductor pair connected to the phones to a second conductor pair normally not used. The system and method further employs a modem which receives telephone signals from the telephone line via the second conductor pair.

Abstract: In an object oriented software environment, a system and method is disclosed that addresses both state recovery and relationship recovery in the event of a system halt. The system is suited to enterprise-class distributed systems with extensive object relationships. Each essential object is saved in persistent storage. Essential values within each object are updated in storage according to a method within each object. After a partial or total halt of the system, the state of the software is reconstructed in a two phase process. In the first phase, the essential objects are restored from persistent storage, along with essential values. In the second phase, a method uniquely implemented by each object will reconstruct non-essential objects and variables. The second phase is ideally tailored to allow the system to be reconstructed even when the underlying hardware or software has been altered.

Abstract: A system and method for low latency multiplexing of real-time and regular data in the same data frame. Real-time data capable of being delivered at regular intervals (such as digitized voice) is multiplexed with regular (non-real-time data) across a communications link (such as a modem connection). The link's existing packet protocol (such as V.42/HDLC) may be extended to provide low latency for the real-time data, with minimal impact on existing data-transfer efficiency. Before each data frame is transmitted, the transmitter determines the time before the next real-time data will become available for transmission. If the real-time data will become available before the data frame will have been completely transmitted, the real-time data may be embedded within the frame as follows. Bit values within the header of the data frame may be used to indicate the offset within the frame of the start of the real-time data.

Abstract: An integrated circuit is formed with minimal encroachment of lightly doped drain (LDD) implants partially due to barrier atoms incorporated along the migration avenues. Nitrogen is incorporated either during the LDD implant or during an anneal cycle following the LDD implant. Nitrogen helps minimize segregation and diffusion of LDD dopants placed adjacent critical channel and gate dielectric areas. Nitrogen is incorporated within a chamber while under pressure so as to minimize the temperature needed to repair implant damage and activate the LDD dopants. High pressure indoctrination of nitrogen is believed to provide the same amount of lattice repair and activation achieved if anneal temperatures were substantially higher.

Abstract: A computer is provided having a system interface unit coupled between main memory, a CPU bus, and a PCI bus and/or graphics bus. A hard drive is typically coupled to the PCI bus. The system interface unit is configured to perform a data integrity protocol. Also, all bus master devices (CPUs) on the processor bus may perform the same data integrity protocol. When a CPU requests read data from main memory, the bus interface unit forwards the read data and error information unmodified to the processor bus bypassing the data integrity logic within the system interface unit. However, the system interface unit may still perform the data integrity protocol in parallel with the requesting CPU so that the system interface unit may track errors and possibly notify the operating system or other error control software of any errors. In this manner processor read latency is improved without sacrificing data integrity. Furthermore, the system interface unit may still track errors on processor reads.

Abstract: A pending tag system and method to maintain data coherence in a processing node during pending transactions in a transaction pipeline. A pending tag storage unit may be coupled to a cache controller and configured to store pending tags each indicative of a coherence state for a data line corresponding to a pending transaction within the transaction pipeline. The pending tag storage unit includes a total amount of storage which is substantially less than an amount required to store tags contained in the full tag array for the cache memory. When a pending tag exists in the pending tag storage unit, the coherence state of the corresponding data line within the cache memory is dictated by the pending tag for snoop operations. Accordingly, data coherence is maintained during the period when transactions are pending, e.g., not yet presented to a processor and cache.

Abstract: An apparatus and method for enabling remotely controlling power status of a remote device. The apparatus monitors information signals being transmitted to the remote device and from such information, determines whether to alter the power status of the remote device. The apparatus may include an uninterruptable power source to enable such remote control during an interrupt of main power to the apparatus.

Abstract: An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.

Abstract: An apparatus for mechanically connecting modular chemical delivery substrate blocks in single layer and/or multiple lower layer configurations via axial and intermediate locations in such a way that all joint locations (including mounting fixtures to a rigid mechanism for mounting purposes) are completely accessible from the top surface of the assembly for fastening or unfastening the joints of the blocks. A design using the method of the present invention and incorporating current semiconductor standards (such as SEMI 2787) dictates specific mechanical dimensions and fastener localities in order to be properly implemented. Use of this top access fastener design results in minimal numbers of substrate joints in a chemical delivery system being affected when removing any one block from the system.

Abstract: A method for determining the default operating mode of a code segment by determining whether an instruction modifies bits in both the upper-order and lower-order halves of a register. A register is set to a known value and an instruction which operates on the register is subsequently executed. After execution of the instruction, it is determined whether the high-order bits of the register have been modified by the instruction. If the instruction modifies the high-order bits of the register, a first default mode is indicated and, if the instruction does not modify the high-order bits of the register, a second default mode is indicated.