Abstract: A memory including various selectively configurable peripherals which provide on-chip low-level control features and a configuration RAM storing bits which both provide unclocked full logic-level outputs to control the selectively configurable peripherals and can also be accessed and read out. That is, each cell in the configuration RAM has two output modes: a digital continuous output, which is provided as a continuous control signal to various peripheral circuits and a selectable analog output which is used to read the information stored in the configuration RAM.

Abstract: In stacked CMOS, a single gate in first level polycrystalline silicon is used to address both an N-channel device in the substrate and an overlaid p-channel device. The p-channel device has self-aligned source and drain regions formed by diffusing a dopant from doped regions underlying them. The doped regions are formed by planarizing a doped insulating layer, and etching the doped layer back to the upper level of the gate prior to deposition of a second polysilicon layer.

Abstract: A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received column address and the stored defective-column-address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever word line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has even been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.

Abstract: The disclosure relates to a method of growing thermal oxide on silicon wherein the oxide is grown at an increased rate, at reduced temperature or a combination thereof. This is accomplished by operating in an hermetic quartz tube capable of withstanding high pressure with steam or oxygen at super atmospheric pressure.

Abstract: Using a method according to one embodiment of the present invention, an EPROM array may be fabricated providing a dense EPROM array.First the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1 to 1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface.

Abstract: A MOS read only memory, or ROM, is formed by a process compatible with standard P-channel or N-channel metal or silicon gate manufacturing methods. The ROM is programmed either after the protective nitride layer has been applied and patterned, usually the last step in the slice processing method before electrical testing of the devices, or after the electrical testing of the devices. All potential MOS transistors in the ROM array are initially at a logic "0" or a logic "1". An electron beam slice printing machine is used to program the selected transistors in the ROM array to change their logic state by exposing the gates of the selected transistors to an electron beam. The gates to be exposed are predetermined by a coding on a magnetic tape which corresponds to the desired ROM code. No electron beam mask is necessary since the beam only exposes in selected areas.

Abstract: N-channel devices are fabricated with lightly doped drain/source extensions in a CMOS process, without the requirement of an extra mask level. A merged mask technique uses an oversized version of the N-channel gates, expanded by two alignment tolerances per side, combined with the regular N+ source/drain mask. The oversized gate photoresist prevents the heavy N+ source/drain implant from counterdoping the previously introduced lightly doped drain blanket implant. In the P-channel regions the N-type LDD extensions are counterdoped by the regular P+ source/drain implant. This high-voltage process provides 20 V parts with 4 micron geometries, scalable to other voltages.

Abstract: Using a process in accordance with the teachings of this invention, an integrated circuit may be fabricated providing refractory metal silicide layers, such as TiSi.sub.2, of differing thicknesses to provide optimal reductions in the sheet resistances of the regions in which refractory metal silicide layers are formed. In one embodiment of the present invention a field effect transistor having a polycrystalline silicon gate is fabricated to provide a gate having optimally minimized sheet resistance and source and drain regions having TiSi.sub.2 layers of the appropriate thickness to avoid punch-through leakage problems.

Abstract: A static random access memory wherein positive feedback is used in the bit line loads. The output of the first sense amplifier stage is fedback to the gates of depletion-made bit line load transistors, to provide positive feedback during the read or write operation. That is, since one of the complementary bit lines which the accessed memory cell is attempting to pull down sees a load impedance which gradually becomes higher and higher, the memory cell can pull down this bit line more rapidly. To accomplish this with stability, the first sense amplifier stage has less than unity open loop gain, and a succeeding sense amplifier stage is therefore used for further amplification.

Abstract: A method for plasma etching of TiO.sub.2, using a mixture of oxygen and a fluorine-bearing species, preferably CF.sub.4. This mixture gives good selectivity over aluminum and photoresist, and approximately unity selectivity over silica or silicon nitride. Use of a chlorine-containing species is also taught by the invention, and will provide different selectivities. The present invention is also useful for etching in the RIE mode.

Abstract: A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.

Abstract: A stacked CMOS structure is disclosed which uses buried N++ source and drain for the non-self-aligned bulk N-channel driver devices together with an oversized polygate on which a non-self aligned P-channel load device is made from a second layer of poly or recrystallized poly. The non-self aligned pair of stacked devices provides increased density of devices per unit area with a simple process at the cost of increased gate to source and gate to drain parasitic capicitances.

Abstract: A CMOS device configuration in which a complete CMOS inverter is contained in the space normally required for a single NMOS transistor of equivalent geometry. A first polysilicon layer of normal thickness and N+ doping is used for the N channel gate, and a second polysilicon layer is deposited conformally over the oxide which encapsulates the first polysilicon layer. The second polysilicon layer is thin and doped p-type. The second layer is only lightly doped initially, and is then doped more heavily by a low-energy implantation. The portions of the second poly layer which are adjacent to the sidewalls of the gate level in first poly will be shielded from the heavy implantation, and will therefore provide relatively lightly doped p-type channel regions, to form a pair of PMOS polysilicon transistors addressed by the N+ first poly gate electrode. Preferably the channel doping of these polysilicon transistors is at least 10.sup.17.

Abstract: A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is selfaligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

Abstract: In order to provide low and exactly repeatable common lead inductance (gate lead inductance) and low feedback parasitics in a common-gate low noise amplifier, a GaAs FET connects the gate electrode to ground at various points along its width by means of an air bridge crossover structure. This structure crosses over the input (source) lines with very low capacitance. Since the gate lead inductance is low in this design, and because in monolithic form this inductance does not vary as is the case for a device grounded using bond wires, common-gate circuit stability is assured. This device preferably uses the well-known pi-gate configuration to provide low drain-gate parasitic capacitance and equal phasing to all parts of the device.

Abstract: A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.

Abstract: In a distributed IMPATT structure, power is coupled out through a side contact. That is, in previously proposed distributed IMPATT structures the gain medium (the active region of the IMPATT) operates as a transmission line. The prior art has attempted to couple output power from the gain medium through an end contact, i.e. through a contact which intercepts the primary direction of energy propagation of the active medium. In the present invention, a side contact extends along the whole active region in a direction which is parallel to the principal direction of propagation of the energy in the active medium. Thus, the side contact plus the active region together can be considered as a single transmission line.The present invention can be configured as an oscillator, amplifier, phase shifter, or attenuator. When configured as an oscillator, multiple short active regions can be sequentially coupled to a single long microstrip, which serves as the side contact for each of the active regions.

Abstract: Hydrogen annealing permits deposition of good quality polysilicon atop TiO.sub.2. Hydrogen annealing of TiO.sub.2 prevents the tremendous hydrogen affinity of as-deposited TiO.sub.2 from disrupting process reactions during deposition of polysilicon.

Abstract: The disclosure relates to a method for removing the unwanted impurities from an HgCdTe alloy which consists of the steps of depositing a thin film on the order of from about 1 to about 100 microns in thickness of tellurium onto the backside of a mercury cadmium telluride bar to insure the presence of a substantial amount of excess tellurium on the backside of the alloy bar and allow the gettering mechanism to work. A protective film to shield the tellurium film from mercury ambient atmosphere is then optionally placed over the tellurium film. The protective film can be formed of a silicon oxide such as SiO and is preferably in the range of about 1000 angstroms to 10 microns or more in thickness. The bar with the tellurium and protective film thereon is then annealed at a temperature of less than 450.degree. C., preferably about 280.degree. C.

Abstract: In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlaid p-channel device. The p-channel polysilicon device has its channel self-aligned to the gate, by the use of a boron-doped oxide at the sidewalls of the gate. This boron-doped oxide provides a dopant source which dopes the second polysilicon layer to provide heavily doped source/drain extension regions which are self-aligned to the gate in first poly. A mask level is still required to pattern the sources and drains, but the self-aligned source/drain extension regions mean that the source/drain mask level can have a reasonable alignment tolerance.