Abstract: A power-down inverter comprising three devices in series between supply voltage VDD and ground. A depletion load transistor connects the power supply rail to a first output node; a natural-threshold-voltage transistor, whose gate is controlled by the power-up signal, connects the first output node to a second output node, and an enhancement mode transistor, whose gate is controlled by the input signal to the inverter, connects the second output node to ground. This circuit provides an output (at the first output node) which is never floating, and it is therefore not necessary to use complementary signals for the power-up information. Moreover, the provision of two output nodes permits multiple output states to be available during the power-down mode if desired, depending on the full circuit configuration.

Abstract: The disclosure relates to a method for making extrinsically doped HgCdTe alloys containing Cu, Ag, or Au or other dopant impurity whereby the excess tellurium in the core is annihilated (stoichiometrically compensated by excess in-diffusing Hg) and the dopant impurities are then permitted to randomly move through the slab to provide for homogeneity thereof. A post-annealing step of much greater than normal temperature-time length than was provided in the prior art is used. A standard post-annealing step in a saturated mercury vapor atomosphere leaves second phase tellurium (and gettered impurities) at the center of the slab, and longer term post-annealing negates this situation by annihilating the second phase tellurium in the slab and thus permitting the impurities to randomly travel by solid state diffusion throughout the slab to ultimately be distributed therein in a homogeneous manner.

Abstract: A very simple oscillator circuit, using a FET pair with RF coupled, DC isolated gates, selectively operates at two widely separated microwave frequencies. The two FETs are DC isolated so that one of them can be pinched off (to act as a passive element) while the other remains active. Thus, for example, a two-FET push-push oscillator operating at 20 GHz can switch downband, when one FET is pinched off, to act as a fundamental mode oscillator at 121/2 GHz. The circuit is integrable. In alternative embodiments, more than two FETs are used, for switching over a wider frequency range when one or two of them is pinched off.

Abstract: An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath a thick field oxide, depletion and enhancement mode device channel implants, implanted source and drain regions, selective oxidation to form self-aligned gates, metal-semiconductor junctions as control elements, barrier metal and a thin film metallization system. The process and device structure are suited for high packing density, very low speed power product and ease of fabrication making it attractive for digital applications.

Abstract: CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region. Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative diffusion effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion.To avoid the erratic etching characteristics of heavily-doped polysilicon under chloro-etch, the patterned photoresist used to pattern the gates and gate-level interconnects is left in place during the P+ source/drain implant. Thus, moderately doped N-type polysilicon may be used, since it is not exposed to compensation by the P+ implant. Since no P+ source/drain mask is required, no double-level photoresist structure is created, and there is consequently no obstacle to reworks.

Abstract: Laser patterning of metallization is done by transmitting laser energy through a liquid film directly in contact with the metallization to be patterned. When the metal is evaporated by the laser energy, the vapor is condensed immediately by the liquid film. This prevents redeposition of metal on the patterned surface and suspends the removed metal in the liquid so that it may be reclaimed by filtration.

Abstract: A non-volatile memory storage cell utilizing a single vertical junction field-effect transistor is fabricated by a method, which is compatible with the fabrication of MOSFET interface and logic circuits on the same chip. Assembly of a multi-dielectric stack, which contains the non-volatile element, is accomplished late in the process to avoid degradation of the non-volatility characteristics.

Abstract: A charge injection device array is fabricated, having one row of devices optically opaqued. Device outputs are read using a correlated double sample technique. The voltage of an entire column of devices with a selected row addressed is measured. The same column of devices is again measured with signal of no row addressed. Therefore, the difference is the charge on the device in the row addressed. The output of each device in a column is referenced to the output of the device in the opaqued row of the column, or a set level, if no row is addressed.

Abstract: A novel metal-oxide-semiconductor (MOS) field effect transistor having enhanced oxide thickness at the edge of the gate electrode and having metal silicide regions in the gate electrode and source and drain areas. The enhanced oxide thickness improves interconnect-to-interconnect breakdown voltage in multilevel interconnect devices as well as minimizing gate overlap of source and drain. The metal silicide regions reduce series resistance and improve device speed and packing density.

Abstract: An epitaxial layer of a narrow-gap semiconductor is deposited on a substrate comprising a wider-gap semiconductor. The opposite surface of the substrate is then illuminated with light pulses at a wavelength corresponding to the desired bandgap of the resulting material. Each pulse causes localized heating where it first encounters a material having a sufficiently narrow bandgap to be an absorber at the wavelength of illumination. This localized heating will then cause interdiffusion, producing a layer of semiconductor alloy having a bandgap intermediate between the bandgaps of the two starting materials. Repetition of this step will have the effect of moving the region of localized absorption away from the original location, and toward the film/air interface. Since the desired end product composition will be transparent to the illumination applied, the process is inherently self-limiting.

Abstract: A HgCdTe film is produced on a CdTe substrate, by depositing HgTe on a CdTe substrate, and then illuminating the substrate from the underside with infrared light at a wavelength longer than the desired operating wavelength (band-gap-equivalent wavelength) of the device. Since CdTe is transparent in the infrared, the light will reach the HgTe/CdTe interface. Since HgTe is an absorber in the infrared, most of the infrared radiation will be absorbed near the interface, which will cause intense localized heating and thus accelerate the interdiffusion of HgTe and CdTe. This interdiffusion will have the effect of moving the interface away from the original location, and toward the film/air interface. Since the desired end-product HgCdTe composition will be transparent to the infrared radiation applied, the process is inherently self-limiting.

Abstract: In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anistropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.

Abstract: A semiconductor read-only-memory (ROM) device having an array of punch-through devices as memory cells. The cells are formed at the crossing points of two pluralities of parallel elongated regions, the two pluralities being perpendicular to each other. One plurality is located in subsurface regions of a semiconductor body and is of a conductivity type opposite that of the surrounding body. The other plurality is located at a surface of the semiconductor body and is of the same conductivity type as the subsurface plurality. The device is programmed by implanting impurities of the same conductivity type as the semiconductor body between selected crossing points. No contacts exists in the array.

Abstract: A CCD imager is provided with an adaptive threshold circuit. The variations in the illumination across the document being read by the imager are compensated for by the adaptive threshold circuit to accurately provide an accurate digital representation of the image on the document.

Abstract: A Modem utilizing process technology compatible CCD and IGFET circuits and sub-systems incorporated on a single I.C. chip. CCD transversal filters are employed as bandpass filters, being tuned for different modes of operation by adjustment of the clock frequency. The bandpass filters are operated in conjunction with a charge amplifier to remove d.c. offset from the analog output of the filters. The demodulator section of the Modem also incorporates low-pass filter employing switched resistors. The modulator section includes waveform generators based on a digital-to-analog converter including switched capacitors having values selected such that a sine wave having minimal distortion is generated when switched in proper sequence. Provision is made for digital inputs to control the frequency and amplitude of the sine wave output. The Modem can be operated under control of a microprocessor.

Abstract: The present invention is embodied in a dynamic random access memory (RAM) cell comprising a depletion mode field effect transistor structure with a p-n junction "gate" electrode. The cell can be programmed to two threshold voltage states providing constant current sensing. Cell programming is by application of appropriate signals to the transistor "gate" electrode and source. Reading is accomplished by sensing current through the transistor while the source is grounded. An intermediate voltage on the "gate" electrode prevents changes in the state of the cell.

Abstract: A method for producing monocrystal on insulator is disclosed. Initially, an epitaxial layer is created on the single crystal substrate. This epitaxial layer may be formed by direct deposition of the monocrystal layer, or through epitaxial monocrystal growth induced after a polycrystal or amorphous layer has been deposited upon the substrate. By appropriately scanning a laser or other focused energy source beginning at some point within the epitaxial layer, and moving into the polycrystalline or amorphous layer over the insulator region, the polycrystalline or amorphous layer will melt, then upon resolidifying it will be monocrystal in structure due to its monocrystal neighbor, the epitaxial layer.