Abstract: A method and apparatus for integrated circuit package thermo-mechanical reliability analysis are described.

Abstract: Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device includes a primary integrated circuit (IC) die and at least one secondary IC die mounted on the primary IC die. A heat extraction element includes a base mounted to the semiconductor device such that each of the at least one secondary IC die is between the primary IC die and the heat extraction element. At least one dummy fill is adjacent the at least one secondary IC die, and each thermally couples the primary IC die to the heat extraction element.

Abstract: Method and apparatus for communicating data between vertically stacked integrated circuits is described. In some examples, a method of configuring an integrated circuit which is a first die includes obtaining configuration data at configuration resources of the integrated circuit from a non-volatile memory on a second die through an integration tile of the integrated circuit, the second die being vertically stacked on the first die; storing the configuration data in at least one register as the configuration data is obtained by the configuration resources; and loading the configuration data from the at least one register to a configuration memory of the integrated circuit to configure programmable resources of the integrated circuit.

Abstract: Method, apparatus, and computer readable medium for designing an integrated circuit (IC) are described. In some examples, layout data describing conductive layers of the integrated circuit is obtained. The layout data is analyzed to identify through die via (TDV) areas. A metal fill pattern is created for each of the TDV areas having a maximum metal density within design rules for the integrated circuit. The metal fill pattern for each of the TDV areas is merged with the layout data.

Abstract: Method and apparatus for controlling an operating mode of an Ethernet media access controller (MAC) embedded in a programmable device is described. In some examples, a configuration circuit is configured to receive a configuration signal from configuration memory of the programmable device and a host signal from a host bus of the programmable device, and configured to output a control length check disable signal the value of which depends on the value of at least one of the configuration signal or the host signal. A parameter check circuit is configured to receive a control signal derived from at least one of the control length check disable signal or the configuration signal, and configured to selectively disable checking a length of each control frame in frames received by the Ethernet MAC based on a value of the control signal.

Abstract: Methods and apparatus for testing packaged ICs are disclosed. In some embodiments, an apparatus for testing a packaged integrated circuit (IC) can include a device handler for moving the packaged IC; a testing station for testing the packaged IC; and a pre-test conditioning station configured to remove at least a portion of an oxidation layer formed on contacts of the packaged IC prior to testing. In some embodiments, a method for testing packaged ICs may include providing a packaged IC to be tested; at least partially removing an oxidation layer from contacts of the packaged IC prior to testing; inserting the packaged IC into an interface structure; and testing the packaged IC.

Abstract: An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit (IC). In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads. Metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads. A description of the layout data is generated on one or more masks for manufacturing the integrated circuit. By maximizing metal density in the superimposed plane, vertical channels through the dielectric material in the interconnect are reduced or eliminated. Thus, alpha particles cannot readily penetrate the interconnect and reach the underlying semiconductor substrate, reducing soft errors, such as single event upsets in memory cells.

Abstract: Method and apparatus for inter-IC communication are described. In some examples, an integrated circuit (IC) includes core circuitry configured to process input data and provide output data; input/output (IO) circuitry configured to receive the input data, and transmit the output data; a control circuit configured to provide a selection signal; and an inter-IC communication port coupled between the core circuitry and the IO circuitry and configured to pass the input data and the output data, the inter-IC communication port having a memory interface and a memory controller, the inter-IC communication port configured to selectively couple either the memory interface or the memory controller between the core circuitry and the IO circuitry responsive to the selection signal.

Abstract: Method and apparatus for modeling processor-based circuit models are described. Some examples relate to designing a circuit model having a processor system and custom logic. A bus adapter coupled to a bus of the processor system is generated. A shared memory interface between the custom logic and the bus adapter is generated. The shared memory interface includes a memory map for the processor system. A clock wrapper having a first clock input and a second clock input is generated. The first clock input drives the custom logic and first shared memory of the shared memory interface. The second clock input drives the processor system.

Abstract: An aspect of the invention relates to modeling a transistor in an integrated circuit design. Layout data for the integrated circuit design is obtained. A geometry relating the transistor to at least one well edge of at least one implant well is extracted from the layout data. An effective well proximity value for the transistor is calculated based on the at least one well edge using a complementary error function. The transistor is modeled using the effective well proximity value. In one embodiment, the effective well proximity value is added to a post-layout extracted netlist for the integrated circuit design. The integrated circuit design may be simulated using the post-layout extracted netlist. The effective well proximity value may be used to calculate a threshold voltage for the transistor during the step of simulating the integrated circuit.

Abstract: Method and apparatus for self-regulated burn-in of an integrated circuit (IC) is described. One embodiment of a method of burn-in for the IC includes: configuring programmable resources of the IC device based on a burn-in pattern to implement a load controller, the load controller having a plurality of heat core circuits. The load controller is initialized with a number of enabled heat core circuits of the plurality of heat core circuits. A junction temperature is measured in the IC device after a measurement period has elapsed. The junction temperature is compared with a set-point temperature. The number of the enabled heat core circuits is increased if the junction temperature is less than the set-point temperature, or the number of the enabled heat core circuits is decreased if the junction temperature is greater than the set-point temperature.

Abstract: A semiconductor device package and methods of manufacturing the same are described. In some examples, a semiconductor device includes an IC die including a ring of die pads around a periphery thereof, lands disposed within the ring of die pads, bond terminals coupled to the lands, the bond terminals being wire-bonded to respective ones of the die pads, and at least one capacitor having respective terminals mounted to respective ones of the lands.

Abstract: An amplifier circuit having a differential input and an amplifier output is provided. In some examples, the amplifier circuit includes a first input stage having a first complementary transistor pair providing a first input and a first output, the first input being a first half of the differential input; a second input stage having a second complementary transistor pair providing a second input and a second output, the second input being a second half of the differential input; an output stage coupled to the first input stage and the second input stage and providing the amplifier output; and a transistor coupled in parallel to one transistor in one of the first complementary transistor pair or the second complementary transistor pair.

Abstract: Method and apparatus for profiling a hardware/software embedded system are described. In one example, a hardware co-simulation interface is generated between a programmable logic device (PLD) configured with the embedded system and a computer based on a plurality of events. The embedded system in the PLD is simulated. During the simulation of the embedded system, occurrence of at least one event is detected to produce profiling data. The profiling data is stored into shared first-in-first-out (FIFO) logic of the PLD and the computer. The profiling data is retrieved from the shared FIFO logic at the computer.

Abstract: Method and apparatus for processing variable-length packets in a buffer memory for transmission are described. In some examples, as each packet of the packets is written to a buffer memory, a length of the packet is obtained from a length field therein. For each packet of the packets, the length of the packet is compared with a threshold length. An encoded length for each of the packets is stored in a sideband memory, the encoded length for each packet of the packets being: (i) the length of the packet if the length satisfies the threshold; or (ii) a predefined value if the length of the packet does not satisfy the threshold. As each packet of the packets is read from the buffer memory, an end location of the packet is determined responsive to the encoded length thereof in the sideband memory.

Abstract: Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with first data; executing a first iteration of the system to process the first data; partially reconfiguring the PLD, during execution of the first iteration, to initialize shadow memory elements in the PLD with second data, the shadow memory elements respectively shadowing the memory elements in the system; transferring the second data from the shadow memory elements to the memory elements; and executing a second iteration of the system to process the second data.

Abstract: A multiplier-accumulator includes a pre-adder, a multiplier, an accumulator, multiplexing logic, and control logic. The pre-adder is configured to sum a first input and a second input to produce a pre-sum output. The multiplier is configured to multiply a third input and the pre-sum output to produce a product output. The accumulator is configured to sum a pair of accumulator inputs to produce a sum output. The multiplexer is configured to select the pair of accumulator inputs from a plurality of multiplexer inputs, where the plurality of multiplexer inputs includes the product output and the sum output. The control logic is configured to control operation of the pre-adder, the accumulator, and the multiplexer logic. In an example, each of the first input, the second input, the third input, and the sum output is coupled to programmable interconnect of a programmable logic device.

Abstract: Method, apparatus, and computer readable medium for producing an optimized matrix triangulation algorithm is described. In one example, tile functions are generated for a matrix triangulation problem. Cost data is measured for the tile functions with respect to a target architecture. The cost data is processed to identify optimal composition of tiles for rows in an iteration space of the matrix triangulation problem. The optimal compositions of tiles are processed to identify optimal composition of rows for triangles in the iteration space. A sequence of tile function invocation based on the optimal compositions of tiles and the optimal compositions of rows is generated.

Abstract: Method, apparatus, and computer readable medium for modeling an integrated circuit in a computer aided design system (CAD) are described. In some examples, a device model of the integrated circuit is generated in at least one first computer file, the device model having a component hierarchy. A common delay identifier is defined for component instances in the component hierarchy of the device model. A value model is generated for the device model in at least one second computer file. Delay values are defined for the common delay identifier in the value model, at least a portion of the delay values being qualified based on location in the component hierarchy of at least one of the component instances.

Abstract: Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.