Abstract: Semiconductor devices having redundant through-die vias (TDVs) and methods of fabricating the same are described. A substrate is provided having conductive interconnect formed on an active side thereof. Through die vias (TDVs) are formed in the substrate between a backside and the active side thereof. The TDVs include signal TDVs, redundant TDVs (i.e., redundant signal TDVs), and power supply TDVs. The signal TDVs are spaced apart from the redundant TDVs to form a pattern of TDV pairs. The power supply TDVs are interspersed among the TDV pairs. The conductive interconnect includes first signal conductors electrically coupling each of the signal TDVs to a respective one of the redundant TDVs defining a respective one of the TDV pairs.

Abstract: Method and apparatus for mapping flip-flop logic onto shift register logic is described. In one example, a method of processing flip-flop logic in a circuit design for implementation in an integrated circuit is provided. A chain of flip-flops in the circuit design is identified. The chain of flip-flops includes first and second control signals. A shift register is instantiated in a logical description of the circuit design for the chain of flip-flops. A shift register is instantiated in the logical description for the chain of flip-flops. First and second control chains of flip-flops are instantiated in the logical description for the first and second control signals, respectively. A multiplexer is instantiated in the logical description and is configured to select among an output of the shift register, an asserted logic state, and a de-asserted logic state based on outputs of the first and second control chains.

Abstract: Method, apparatus, and computer readable medium for implementing a circuit model in an integrated circuit are described. In some examples, the circuit model includes a communication channel between actors. Data portions of at least one data object passed between the actors over the communication channel are identified. An implementation is generated for the circuit model in which data portions are assigned to either local queue storage of the communication channel or centralized shared storage of the communication channel based on levels of access thereof by the actors.

Abstract: Methods for making and testing a semiconductor device with through substrate vias are described. In some examples, a method of making a semiconductor device includes: forming through substrate vias (TSVs) in a substrate having an integrated circuit (IC) die, the substrate including an active side and a backside, the active side having conductive interconnect formed thereon, the TSVs including exposed portions on the backside of the substrate; patterning first metal on the active side of the substrate to electrically couple the TSVs to a portion of the conductive interconnect; and coupling the exposed portions of the TSVs on the backside of the substrate to electrically couple together the plurality of TSVs.

Abstract: Method and apparatus for communication between a processor and processing elements in an integrated circuit (e.g., a programmable logic device is described. In an example, a first lookup table is configured to store first information representing which of the processing elements is capable of performing which of a plurality of instructions. A second lookup table is configured to store second information representing which of the plurality of instructions is being serviced by which of the processing elements. Control logic is coupled to the processor, the first lookup table, and the second lookup table. The control logic is configured to communicate data from the processor to the processing elements based on the first information, and communicate data from the processing elements to the processor based on the second information.

Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.

Abstract: Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.

Abstract: Method and apparatus for interfacing a programmable circuit and a processor is described. In one example, data output from the programmable circuit is packetized to form at least one packet. The at least one packet is provided to the processor via a streaming interface. The data is extracted from the at least one packet. A function is executed on the processor using the data as parametric input. Return data is then packetized by the function in response to the parametric input to produce at least one return packet. The at least one return packet is send towards the programmable circuit via the streaming interface. The return data is extracted from the at least one return packet and provided to the programmable circuit.

Abstract: Method and apparatus for detecting clock loss in clock circuit. An example of the invention relates to detecting loss of a feedback clock signal input to a digital clock manager, where the feedback clock signal is derived from the reference clock signal. A clock divider is provided to produce a divided feedback clock signal from the feedback clock signal. A first pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of the reference clock signal. A second pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of an inversion of the reference clock signal. Detection logic is configured to detect whether each of the first pair of flip-flops and each of the second pair of flip-flops store the same value.

Abstract: Method and apparatus for processing scalable content having a base layer and at least one enhancement layer is described. In one example, static logic having decoder logic and system monitor logic is provided. Programmable logic having a plurality of reconfigurable slots is also provided. The decoder logic includes a base layer processor for processing the base layer of the scalable content. The system monitor logic is configured to dynamically reconfigure at least one of the plurality of reconfigurable slots with at least one enhancement block for processing the at least one enhancement layer of the scalable content.

Abstract: Method, apparatus, and computer readable medium for performing electrical rule checks (ERCs) on a circuit design are described. In one example, a hierarchy of cell instances is created from a schematic database for the circuit design. The hierarchy is traversed to produce master nets. Each of the master nets is associated with shorted nets in the circuit design. The hierarchy is traversed to produce ERC nets. Each of the ERC nets is associated with effectively shorted nets in the circuit design. At least one pair of the effectively shorted nets is effectively shorted across a transistor. At least one ERC is performed on the circuit design using the master nets and the ERC nets.

Abstract: Method and apparatus for designing an embedded system for a programmable logic device (PLD) is described. Parameters specific to the embedded system are obtained. Source code files that use the parameters to define configurable attributes of the base platform are generated. A software definition and a hardware definition are obtained. The software and hardware definitions each use an application programming interface (API) of the base platform to define communication between software and hardware of the embedded system. An implementation of the embedded system is automatically built for the PLD using the source code files, the software definition, and the hardware definition.

Abstract: Methods and apparatus for configuring a programmable integrated circuit are described. In one example, a configuration stream having first data for programming first locations in a configuration memory and an instruction for referencing circuitry in the programmable integrated circuit is received. Second data is obtained from the circuitry based on the instruction. Second locations in the configuration memory are programmed in response to the second data.

Abstract: Method and apparatus for providing secure intellectual property (IP) cores for a programmable logic device (PLD) are described. An aspect of the invention relates to a method of securely distributing an IP core for PLDs. A circuit design is generated for the IP core, the circuit design being re-locatable in a programmable fabric for PLDs. The circuit design is encoded to produce at least one partial configuration bitstream. Implementation data is generated for utilizing the IP core as a reconfigurable module in top-level circuit designs. The at least one partial configuration bitstream and the implementation data are delivered to users of the PLDs.

Abstract: A scan element with self scan-mode toggle is described. In an example, the scan element is configured to automatically switch between a capture mode and a scan mode. In the capture mode, data is captured from logic under test. In the scan mode, the captured data is scanned out for testing. The scan elements each include a shift register that serves a dual purpose of providing control for determining when the scan element is to switch from the capture mode and the scan mode, as well as providing a location to store captured data.

Abstract: A method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.

Abstract: Method and apparatus for initializing an integrated circuit are described. A static memory includes an array of memory cells having control lines coupled to a column select component and data lines coupled to a register component. The static memory is formed in one or more first process layers of the integrated circuit. A non-volatile memory includes an array of non-volatile memory cells disposed between column electrodes and row electrodes. The non-volatile memory is formed in one or more second process layers of the integrated circuit disposed above the one or more first process layers. An interface circuit is configured to couple the column select component to the column electrodes and the register component to the row electrodes.

Abstract: A method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.

Abstract: Method and apparatus for detecting a bit sequence in a data stream is described. In one example, a first memory is configured to process pairs of bit-patterns in the data stream to provide respective pairs of codes from a code table stored in said first memory. A second memory is configured to process pairs of codes from the first memory to provide combination codes from a combination code table stored in the second memory. A third memory is configured to generate detection data in response to a sequence of the combination codes output from the second memory. The first, second, and third memories may be dual-port synchronous memories, such as block random access memory embedded in an integrated circuit. The data stream may be a serial digital interface (SDI) data stream and the bit sequence may be a timing reference signal.

Abstract: Method, apparatus, and computer readable medium for directed physical implementation of a circuit design for an integrated circuit is described. One aspect of the invention relates to implementing a circuit design for an integrated circuit. Matching elements between an original version of the circuit design and a modified version of the circuit design are identified. The original version includes an original implementation. The modified version is partially placed and routed to establish a guided implementation having guided placements and guided routes for the matching elements based on placements and routes from the original implementation. Actual timing characteristics for the guided placements and the guided routes are obtained. Since the routes in the guided implementation are fully implemented, actual timing characteristics can be exactly determined. Placement and routing in the modified implementation are completed using the actual timing characteristics.