Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a group clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant group of the checksum register. A group wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the groups of CRC data can be shifted into position through the array one group per each cycle of the group clock.

Abstract: There is disclosed herein an apparatus and method for generating a first signal related to the rate of change of a second signal. In particular, a system is disclosed for generating a velocity signal in a sampled data servo system. The apparatus uses three track and hold amplifiers one of which is also a difference amplifier to sample the position error signal at selected times. A "present" track and hold amplifier samples and holds the position error signal during the current frame. After this is done, during the same frame, a "summing" track and hold amplifier having its difference inputs coupled to the outputs of the "present" track and hold amplifier and to a "previous" track and hold amplifier samples the difference between the present position error signal and the value of the position error signal during the previous sample frame. This difference divided by the sample period gives the velocity.

Abstract: There is disclosed herein an up/down counter with a programmable terminal count. The up/down counter has a two level input structure such that new terminal counts may be written into the up/down counter asynchronously without disturbing operations of the up/down counter. Although the invention is described in the bidirectional sense, certain of the features are also applicable to unidirectional counters.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus used 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.

Abstract: There is disclosed herein a servo data demodulator for use in magnetic head positioning servo system for disk drives. The demodulator is comprised of a single peak detector which detects the maximum amplitude of the peaks in an input signal during specific times. A storage capacitor is used in the peak detector to store the peak level. This peak level is sampled a predetermined number of times during each data frame. Each sample is taken by a different sample and hold circuit, and the sequence of the samples is controlled by a timing generator. The capacitor of the peak detector is discharged by a switch controlled by the timing generator after each sample and before the next sample. The time delay before the first sample from the start of the frame and the sample time in the sequence is programmable by the user by setting certain inputs into the timing generator.

Abstract: There is disclosed herein an apparatus and method for accurately ascertaining the time of occurrence of passage of the leading and trailing edges of an input pulse through the 50% amplitude level. The apparatus implements the transfer function 1 - cos(wt) where t is equal to the round trip delay through a delay line, and w is the angular velocity of each fourier component of the input signal. In one embodiment, a summing resistor and a delay line having a characteristic impedance equal to that of the resistor are used. The output of the delay line is coupled to one input of a comparator, and the other input is coupled to the junction between the summing resistor and the delay line. Another embodiment uses two matched delay lines, two factoring circuits, a summing circuit and a comparator to implement the same transfer function.

Abstract: Structure is disclosed for a charge-coupled device for generating reference signals indicative of black and white optical conditions and for generating an end-of-scan indicator signal. The black reference signal is generated by electrically and optically isolating one or more photosites of the CCD. A white reference signal is generated by injecting a controlled amount of charge into one or more elements of a shift register of a charge-coupled device. The end-of-scan indicator signal is generated by injecting a signal into at least one element of a shift register which does not have photosites associated with it. The black and white reference signals allow the utilization of the full dynamic range of the device under a wide range of operation conditions, while the end-of-scan indicator eliminates the need for external counting or reset circuits associated with conventional charge-coupled devices.

Abstract: A process and structure are disclosed which are suitable for forming large arrays of Schottky diodes at desired locations between mutually perpendicular strips of aluminum and strips of metal-silicide. The invention is particularly useful in creating read-only memories and programmable logic arrays, and allows fabrication of Schottky diodes more compactly than previous structures.

Abstract: An improved liquid handling device used for transferring a selected quantity of liquid from one receptacle to another. The device includes a meniscus tracking feature which minimizes mixing in a liquid sample and contact between the sample and a sample-handling pipette during a liquid-transfer operation. Further included is a volume-correcting feature for improving the accuracy of volume withdrawn into or dispensed from the pipette during a liquid handling operation.

Abstract: A process is described for fabricating spacers of a desired thickness of filters, the spacers to be used in separating the filter from an underlying image sensing device. The process includes the steps of forming a pattern of electrically conductive material on one surface of the filter, depositing dry resist to the desired thickness over all of the filter except on the electrically conductive pattern, depositing additional electrically conductive material on at least the electrically conductive pattern, and removing the dry resist.

Abstract: A power MOSFET semiconductor structure is fabricated using the steps of depositing an epitaxial layer 12 of N conductivity type silicon on an underlying silicon substrate 10 of N conductivity type, forming a plurality of polycrystalline silicon electrodes 18 on the epitaxial layer 12, each electrode 18 being separated from the epitaxial layer 12 by a layer of insulating material 15; introducing P 30 and N 33 conductivity type impurities into the epitaxial layer 12 between the electrodes 18, the P type impurity 30 underlying the N type impurity 33; removing regions of the epitaxial layer 12 to form openings 21 in the epitaxial layer 12 between the electrodes 18, the removed regions 21 extending through the N type region 33 but not through the P type region 30; and depositing electrically conductive material 40 in the opening 23.

Abstract: A CMOS buffer for the dynamic translation of input signals at TTL levels to corresponding signals at CMOS levels. A reference voltage at a level between the 0.8 volt maximum TTL "0" input level and the 2.4 volt minimum "1" input level is generated by charge distribution between capacitors. This reference level is compared with an input signal level in a dynamic comparator comprised of a CMOS cross-coupled latch to produce output signals at CMOS levels that correspond to the TTL input signals.

Abstract: In a capacitive storage integrated circuit dynamic random access memory having a cross-coupled transistor sense amplifier coupled to a bit line wherein capacitive storage cells are coupled to the bit line through transistor transfer gates, means are provided for restoring charge on the capacitive storage cell by recharging the memory cells directly rather than through the bit lines. Specifically, each storage cell has one terminal coupled to one electrode terminal of the transistor transfer gate and its other terminal coupled to a switched voltage reference. The storage cell is not referenced to a fixed ground level.

Abstract: A lateral bipolar transistor having a base width of 0.