Abstract: A structure and method for implementing a fully digital frequency difference detector uses an n-bit counter to count cycles of a reference clock signal and an m-bit counter to count cycles of a synthesized clock signal, where m is greater than n. The two counters operate concurrently, and both are halted when the n-bit counter overflows into its nth bit position. Two latches respectively record if bits n and (n+1) in the m-bit become set prior to the n-bit counter overflowing. By observing the state of the two latches and the state of a predefined bit range within the m-counter, the frequency difference detector can determined if the frequency of the synthesized clock is greater than, less than, or locked to the frequency of the reference clock signal.

Abstract: An unpartitioned high-speed 8B/10B encoder and corresponding methods use only one edge or level of the clock signal per clock cycle to encode a set of 8B to a corresponding set of 10B data, and thus is not limited to a 50% clock duty cycle. The encoder includes an unpartitioned encoding circuit that receives 8B data and a special character signal and generates 10B intermediate data, a disparity control that receives the 8B data and the special character sign in parallel with that information being received by the encoding circuit, and also receives a clock signal, and generates two control signals; and logic circuitry that receives the intermediate output data and the two control signals and generates the 10B output data. The encoder may be embodied in a high-speed encoding system in which the processing speed of the encoder is greater than 250 MHz.

Abstract: An internet presentation system includes an internet accessible server that permits specific types of access to a target presentation file by selected remote users. Only users having purchase access to the target presentation file may submit a purchase order for a copy of the presentation file. Each user is further restricted to the type of copy, video or data, of the presentation that the user can acquire. Users having purchase permission are further divided into owner status and buyer status. Users having owner status may grant or revoke the purchase permission of non-owner status users. At least one owner status user is additionally designated a super-owner, and can grant and revoke the owner status of other users. The super-owner user may relinquish its super-owner status to any other user.

Abstract: A frequency analyzer carries out a frequency analysis on a pulse wave signal output from a pulse wave detector. A candidate extractor extracts candidate spectrum peaks from a frequency analysis result of the frequency analyzer. A phase variation calculator calculates variations in phase angle of each of the extracted candidate spectrum peaks, and a spectrum peak selector selects a target spectrum peak from among the extracted candidate spectrum peaks based on their respective variations in phase angle. A pulse rate is calculated using the target spectrum peak.

Abstract: A multiplex driving method and driving apparatus are provided for a liquid crystal display device having a liquid crystal layer disposed between a pair of substrates, a plurality of row electrodes arranged on one of the substrates and a plurality of column electrodes arranged on the other substrate, the plurality of row electrodes being arranged in plural groups. A portion of the row electrodes are simultaneously selected a within a selection period in which the selection period is divided into a plurality of intervals. A weighted voltage is applied in accordance with desired display data in each of the plurality of intervals to achieve a gray scale display.

Abstract: In an analog electrical timepiece with a motor coil, when an external operating member is in a prescribed operating condition, the operating mode of the analog electrical timepiece is set to the data receive mode. Next, the analog timepiece generates a synchronization signal which is in synchronized to an external synchronization signal that is input from outside. Then, the analog electrical timepiece, when the operating mode is the data receive mode by the detection circuit, based on a synchronization signal and a data voltage signal that is a voltage signal induced around the motor coil by a data signal input from outside, generates and outputs a receive data.

Abstract: A time measurement device includes a power generator 2, secondary power source 31, current time counters 922 and 932, receiver circuit 42 for receiving a time standard radio wave, time display means 5 for displaying the current time, power detector 83 for outputting a power detection signal when the power generator 2 is in a power generating state or when a voltage stored in the secondary power source 31 is at a predetermined voltage value, operation mode switcher 874 switching, in response to the power detection signal, between a power saving mode in which time display is suspended and a standard mode in which time display is not suspended. The operation mode switcher 874 causes the time display means 5 to display the current time based on the time information counted by the time counters 922 and 932 and the time information received by the receiver circuit in response to the device being switched from the power saving mode to the standard mode.

Abstract: A rectangular vibrating plate 10 in which a piezoelectric element and a reinforcing plate are stacked is supported on a main plate by a support member 11, and is urged toward the rotor 100 by an elastic force of the support member 11. This brings a projection 36 provided on the vibrating plate 10 into abutment with an outer peripheral surface of the rotor 100. In this construction, when the vibrating plate 10 vibrates in the horizontal direction in the figure by an applied voltage from a driving circuit (not shown), the rotor 100 is rotated in a clockwise direction in accordance with the displacement of the projection 36 due to the vibration.

Abstract: A watch has a crown for manual time adjustment, a receiver for receiving current time update signals by radio transmission, an internal counter for counting the passage of time according to an internal oscillator, and time display hands. The watch preferably does not have a means for determining the position of its time display hands and therefore relies on user intervention for roughly correlating its time display hands to its internal counter. Preferably, the user begins a manual time correction operation when the second hand is at a predetermined position between 0-60 seconds. When the crown is pushed in, the seconds count value of the internal counter is reset to the predetermined position, and the watch waits for reception of a current time radio signal. When a radio signal is successfully received, the received seconds value is compared to the seconds count in the internal counter.

Abstract: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

Abstract: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

Abstract: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

Abstract: An electronic timepiece with date display function reduces power consumption in conjunction with the user adjusting the date, and makes it easier for the user to set the date. A displayed date detection unit H has a day detector H1 for detecting the displayed day, a month detector H2 for detecting the displayed month, and a year detector H3 for detecting the displayed year. A control unit A controls a calendar mechanism drive unit F according to the date detected by detectors H1 to H3.

Abstract: A local user issues recording instructions via the Internet to a remote computing device. The remote recording device records broadcast programs available to it according to the received recording instructions, and compresses and encodes the recorded program into a specified media format. The file holding the encoded broadcast program may be subdivided into multiple smaller files before being moved into another computer specified by the user and accessible via the Internet. The remote computing device may receive recording instruction via a pulse telephone and may be incorporated into existing video cassette recorders.

Abstract: An output device can be quickly and easily set to the operating parameters required for a particular output process according to data received from a host device. The output device has RAM that temporarily stores the operating parameters, a memory initialization processor that initializes the volatile memory in response to a specific input, a controller that stores operating parameter values for controlling the output device into the RAM in response to one or more first commands from the host device. A second command from the host device causes a first operating parameter controller to save the operating parameters from RAM into a flash ROM. A second operating parameter controller responds to a third command from the host device by storing information into the flash ROM indicative of whether operating parameter data in the flash ROM should be automatically loaded after the memory initialization process.

Abstract: A status data transmission control apparatus and method reduces the buffer size needed for transmission and significantly reduces the communication load by storing the most recent status data (of continuously generated status data) and a history of status data changes in a dedicated buffer. The most recent status data and the history of changes leading up to the most recent status data are sent to the host.

Abstract: A method of tracking modifications of specific program objects during the runtime of a computer program, facilitates the creation of general UnDo and ReDo operations, as well as the support of an object-specific UnDo operation. When an object is modified, the object is interrogated to collect information about it and how the modification may be undone. The collected information is stored in a highly unbalanced data-tree structure. Since the interrogation of an object is a characteristic of the programming language, and not necessarily a modification of the program being executed, the present method may be easily applied to different existing programs with minimal, if any, modification to the existing programs.

Abstract: A local user issues recording instructions via the Internet to a remote computing device. The remote recording device includes a computer daughter board that records broadcast programs available to it according to the received recording instructions and encodes the recorded program into a specified media format. The daughter board further adds a first field identifying the user and a second field listing some of the received recording instructions on the recording. If the recording is video, then the fields are placed on visible sections of the recording. The file holding the encoded broadcast program may be subdivided into multiple smaller files before being moved into another computer specified by the user and accessible via the Internet. The remote computing device may receive recording instruction via a pulse telephone and may be incorporated into existing video cassette recorders.

Abstract: A soft alumite is produced by forming an oxide film on the surface of an aluminum substrate. Printing is performed on a porous layer formed on the surface of the soft alumite while heating the soft alumite. Alternatively, printing is performed with a dye-based ink on a porous layer formed on the surface of the soft alumite.

Abstract: An electronically controlled timepiece includes an analog circuit (160) driven by a power source (22), a logic circuit (170) driven by a constant voltage regulator circuit (161) forming part of the analog circuit, an oscillator circuit (51) driven by the constant voltage regulator, a power source switch (162) for cutting off the supply of power to the analog circuit other than the constant voltage regulator circuit from the power source during a time correction operation, and a clock cutoff gate (171) for cutting off a clock input from the oscillator circuit to the logic circuit. During the time correction operation, power consumption is reduced because only the oscillator circuit and the constant voltage regulator circuit are operative. The oscillator circuit is not suspended, and an error in time display is eliminated.