Abstract: A large, fault tolerant, highly reliable semiconductor data storage system (memory) is designed to have the memory function striped across multiple symbol planes which comprise individual fault containment regions. Each fault containment region includes such a symbol plane which, in turn, stores at least one bit of any given memory word accessed in the system. The system further includes a processing core module, including at least symbol plane addressing controls, and a channel adapter is provided for selectively connecting the memory to high speed communications channels for, in turn, communicating with client processors or other functional entities attached to the data store system. The processing core contains an error correction/detection mechanism for the error checking and correction of all data fetched from the memory and for generating error correction and detection code bits for all data to be stored in memory.

Abstract: A locking mechanism is incorporated in a high-resolution video display system including a monitor, a computer for providing controls signals to said display system and two frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer.

Abstract: A character recognition system and method using the generalized Hough transform are disclosed. A template table which stores edge point parameters to be used for the generalized Hough transform is compressed so as to include only predetermined parameters, and is then divided into a plurality of template tables which are respectively loaded in the memories of a plurality of subprocessors operating in parallel under the control of a main processor. In performing recognition processing, these subprocessors operate in parallel according to their related partial template tables. Character recognition using the generalized Hough transform provides a high rate of character recognition. Also, parallel processing using the compressed template tables and partial template tables helps shorten table search time and computation time, thereby increasing processing efficiency.

Abstract: A solid state microwave generator is utilized as an excitation source for material/ plasma processes. The invention provides very close precise control of the solid state device's power levels to control the ultimate power output and frequency which control is not readily possible with vacuum tube devices. Utilizing the concepts of the invention the total power generated by the system may be easily varied and, further, the power may be easily monitored and used to control other device parameters such as frequency and the like. Because of the degree of control possible within the overall process system of the invention any measurable physical property of the process such as temperature, power, color (e.g., optical pyrometer), or the like that can be monitored and converted to a control signal can be utilized by the present system to carefully control the overall process conditions. These control features are lacking in currently available vacuum tube microwave devices.

Abstract: An electronic computer system including a central processor and a hierarchical memory system having a large relatively low speed random access system memory and a small high speed set-associative cache memory including a data store section for storing lines of data from the system memory and a cache directory for indicating, by means of line identifier fields at any time, the lines of the system memory data currently resident in cache, is provided with a way to improve the distribution of data across the congruence classes within the cache. A mechanism is provided for performing a permutation operation on an M bit portion (X) of the system memory address, which permutation determines the congruence class into which the address will map. The permutation mechanism performs a bit-matrix multiplication of said M-bit address with an M.times.M matrix (where M is a real positive integer greater than 1) to produce a permuted M-bit address (X').

Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor.

Abstract: An aperiodic mapping procedure for the mapping of logical to physical addresses is defined as a permutation function for generating optimized stride accesses in an interleaved multiple device system such as a large, parallel processing shared memory system wherein the function comprises a bit-matrix multiplication of a presented first (logical) address with a predetermined matrix to produce a second (physical) address. The permutation function maps the address from a first to a second address space for improved memory performance in such an interleaved memory system. Assuming that the memory has n logical address bits and 2.sub.d separately accessible memory devices (where d.ltoreq.n) and a second address that utilizes n-d bits of the first address as the offset within the referenced device node. The procedure includes performing a bit matrix multiplication between successive roows of the said matrix and bits of the first address to produce successive d bits of the second address.

Abstract: A method for compressing an LR, LALR, or SLR parsing table into a compact and time-efficient representation which is machine and language independent, and allows access to table entries with a constant number of primitive operations. The primitive operations used: addition, comparison, and vector indexing, are in general very efficiently implemented on most machines, and are the key to the superior time performance of this method over other methods. Transformations are applied to the parsing table prior to compression.

Abstract: A cursor control/data input device for a computer display system which utilizes a conventional X-Y mouse provided with a third Z with axis data generating mechanism. The mouse may be used with any non-specific support surface and would have conventional X-Y data generating wheels or a rotating ball with appropriate pick-up elements to generate the X-Y coordinate data. Third, or Z, coordinate data is produced by a third instrumentality in the mouse body, preferably operable by the operator's thumb or index finger. Means comprising a pressure sensitive button mounted on the surface of the mouse, or alternatively means actuated by the insertion of the operator's finger into a hole provided in the mouse's body, generate said Z coordinate data. Movement of the finger in the hole is measurable by any of a number of different instrumentalities.

Abstract: A stylus and table X-Y data input system for a video display system. The pen includes an optical styling having a suitable pickup mechanism and the tablet is passive in nature and provides direct digitized data readout. Absolute positional information is encoded in binary form in the tablet in such a fashion that the pen position upon the tablet is automatically determinable by illuminating a particular area of the tablet and reading off the digitized X-Y coordinate data stored therein. The pen and supporting hardware/software are rotationally insensitive so that the pen may be held in any desired position comfortable to a user. The system provides greatly improved resolution, sampling rate accuracy and general robustness particularly for such applications as text recognition as well as a wide variety of other graphical input uses.

Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection mechnaism is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either the first or second memory network contingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements.

Abstract: An interface architecture for interconnecting a plurality of video display devices together over a high speed digital communication link having limited bandwidth provides at each node for transmitting during a "transmit mode"; (1) sequential pixels of digital data (COMVIDOUT) comprising separate luminance and chrominance fields, from a digital TV source associated with each display node which data represents a scaled video window, (2) the local system clock (SCLK), (3) vertical and horizontal communication sync signals (COMVSOUT and COMSHOUT), (4) luminance and chrominance clock enable signals (COMYOCE and COMCOCE) based on a scaling algorithm utilized in the transmitting video device to insure that both the proper pixels and the proper luminance and chrominance fields associated with these pixels are selected by the communications device for transmission.

Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture of the internal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units.

Abstract: A process for forming chromium dioxide thin films which are receptive to high density magnetic recording. The process comprises depositing both chromium and oxygen on a substrate by evaporative techniques and concurrently bombarding the substrate with high energy ions of at least one of the film constituents to form a latent CrO.sub.x film forming layer. The process is carried out at approximately room temperature.The as-grown latent film forming layer is subsequently heat treated by a rapid thermal anneal step which raises the temperature of the as-grown film to about 500.degree. C. The rapid thermal anneal step preferably comprises a series of at least five separte pulses over a 10-second time span. After the rapid thermal anneal, the sample is rapidly quenched to room temperature.

Abstract: An on-chip VLSI cache architecture including a single-port, last-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally integrated units on-chip in addition to the cache array and including a normal read/write CPU access function which provides an architectural organization for allowing the chip to be used in (1) a fast, "late-select" operation which may be provided with any desired degree of set-associativity while achieving an effective one-cycle write operation, and (2) a cache reload function which provides a highly parallel store-back and reload operation to substantially reduce the reload time, particularly for a store-in cache organization.

Abstract: A frame buffer memory organization which is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. The writing of individual pixels in this array is enabled by energizing the write enable pins to each memory chip directly.The data wires in the memory organization are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same.The frame buffer includes a selectively energizable plane mask for disabling desired planes of accessed pixels.

Abstract: A method and apparatus for controlling access to its general purpose registers (GPRs) by a high end machine configuration including a plurality of execution units within a single CPU. The invention allows up to "N" execution units to be concurrently executing up to "N" instructions using the GPR sequentially or different GPR's concurrently as either SINK or SOURCE while at the same time preserving the logical integrity of the data supplied to the execution units. The use of the invention allows a higher degree of parallelism in the execution of the instructions than would otherwise be possible if only sequential operations were performed.A series of special purpose tags are associated with each GPR and execution unit. These tags are used together with control circuitry both within the GPR's, within the individual execution units and within the instruction decode unit, which permit the multiple use of the registers to be accomplished while maintaining the requisite logical integrity.

Abstract: A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data.

Abstract: A mouse for use in a video display system for controlling cursor movement on a display screen provided with feedback means which produces resistance to the motion of the mouse as the cursor moves across predetermined areas of the display screen. In its most straight forward realization it comprises an electromagnet and control circuit which operates independently of the pickup and location sensing control of the mouse to produce a magnetic field which acts cooperatively with a substantially planar magnetic surface to produce a resistance to the motion of the mouse when energized.

Abstract: An etching/deposition system comprising a hollow cathode electron source in combination with a magnetron sputter deposition plasma device within a containment chamber, said hollow cathode being disposed to inject electrons into the magnetic field of the magnetron plasma device adjacent to the magnetron cathode surface to which a deposition source is affixed. Said system further includes means for initiating and maintaining a discharge plasma within the hollow cathode and for initiating and maintaining the magnetron plasma. The improvement of the invention comprises a workpiece to be coated, located in said chamber, spaced from said magnetron cathode surface which may be biased to attract particles emitted by said deposition source.