Abstract: In one embodiment, a plurality of atomic charge pumps (52, 54, 56) are connected together in series to form a distributed charge source (24). The atomic charge pumps (52, 54, 56) are operated sequentially over time to reduce supply signal noise. In addition, the distibuted charge source (24) is compatible with low power applications because each atomic charge pump (52, 54, 56) can be independently powered down if it is not required.

Abstract: A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c′, 32c″).

Abstract: A method and apparatus for display, having a tailpipe attachment piece, adapted for coupling to the exhaust pipe of a vehicle, a receiver piece coupled to the tailpipe attachment piece, wherein the receiver piece is adapted for coupling to a display piece. In one embodiment, a pollution detection device includes a tailpipe attachment piece, a receiver piece coupled to the tailpipe attachment piece, and a chemical indicator coupled to the receiver piece, wherein the chemical indicator is sensitive to the chemistry of emissions. In one embodiment, a method of presenting an advertisement message is provided by attaching the message to the exhaust pipe.

Abstract: A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorphous tantalum nitride layer. A collective thickness of the tantalum nitride and titanium nitride layers 12 and 14 is roughly 400 angstroms or less. A copper material 16 is then deposited on top of the amorphous titanium nitride wherein the composite tantalum nitride layer 12 and titanium nitride layer 14 effectively prevents copper from diffusion from the layer 16 to the layer 10.

Abstract: A data processing system (10) includes a mechanism for preventing DST line fetches from occupying the last available entries in a cache miss queue (50) of the data cache and MMU (16). This is done by setting a threshold value of available cache miss queue (50) buffers over which a DST access is not allowed. This prevents the cache miss queue (50) from filling up and preventing normal load and store accesses from using the cache miss queue (50).

Abstract: A method for forming a semiconductor device in a semiconductor device manufacturing apparatus (20) having a sensor (30) activated extensible shuttle (28). In a fabrication environment shuttle (28) is housed within semiconductor device manufacturing apparatus (20), where an outer door (32) is closed flush with an outer wall of the apparatus (20). As a substrate carrier (38) is moved near the apparatus (20), sensor (30) activates opening of outer door (32) and extension of shuttle (28) out of the apparatus (20) into the fabrication environment. In one embodiment, shuttle (28) has a sensor which is used to determine if carrier (38) is placed on shuttle (28) within a predetermined time, allowing retraction of shuttle (28) until it is required. The present invention increases the available operative space within the fabrication environment, and provides a clean mini-environment within apparatus (20).

Abstract: An integrated circuit memory having a plurality of memory cells, output timing control means including frequency measurement means providing a frequency measurement count corresponding to a first frequency of the external clock signal and delay control means generating a delayed clock signal at the first frequency, wherein the delayed clock signal is delayed in time from the external clock signal in proportion to the first frequency, and data output control means outputting data from the plurality of memory cells responsive to the delayed clock signal. A method for adjusting output timing in a memory device including the steps of receiving an external clock signal, measuring a frequency of the external clock signal, generating a frequency count, determining an output delay proportional to the frequency, and generating an output clock at the external frequency and delayed from the external clock signal in proportion to the frequency.

Abstract: A method and apparatus for performing DMT frame synchronization in an ADSL system begins by providing a training signal (82) to a receiver of the ADSL system (34). The training signal (82) is processed to result in a desired impulse response. The impulse response is used to reduce inter-symbol interference between time-adjacent DMT frames (100-108). The desired impulse response is used to calculate a frame misalignment value (.DELTA.T). The frame misalignment value (.DELTA.T) of the desired impulse response (84) is then utilized to adjust an internal counter of the receiver to perform frame alignment. The use of the training signal (82) and impulse response (84) to provide for both intersymbol interference reduction (FIG. 5) and frame synchronization (FIG. 8) provides for fast ADSL initialization.

Abstract: A method of detecting defective CMOS devices by quiescent current (IDDQ) behavior using a monitor circuit resident in the expendable areas of a die and/or wafer. One embodiment of the present invention incorporates a monitor unit (10) into the scribe grid of a wafer, where pads (2, 3, 4) are built in the corners of the die (5) and connected to the monitor unit (10) via metal connects in the wafer. The monitor unit (10) determines defective die based on IDDQ as expressed by decay of voltage (Vdd) in time, where Vdd is supplied to a die by way of a switch (20) in the monitor unit (10). Alternate embodiments incorporate various configurations and incorporate functional and other tests into a wafer level test system. Other embodiments provide the monitor unit on the die, allowing for later testing and user confirmation.

Abstract: A bond post configuration for wire bonded semiconductors has bond posts grouped in three posts where two are arranged closely to a side of a die about a first axis and a third is arranged in between and further removed from the side about a second axis. In one form, the bond post configuration is a radial configuration. Additionally, conductive traces which extend from the bond posts and away from the die are placed off-center from the the bond posts about the first axis to provide more placement area for the bond posts arranged about the second axis. The bond post configuration may be utilized in any wire bonded semiconductor.

Abstract: A method for recovering the clock in an ADSL (asymmetric digital subscriber line) communication system at the receiver to match the frequency of the transmitted signal. A digital phase locked loop (DPLL) based clock is used to adjust the frequency of data read accesses from a FIFO (first-in first-out) memory (26) in a transceiver unit. The frequency is adjusted according to a predetermined offset value, where the offset value indicates the relative difference between a read location in the FIFO memory (26) and a write location. The predetermined offset value defines an operating point or nominal data location in the FIFO memory (26). A FIFO phase detector (31) determines and affects the frequency adjustment to maintain the FIFO memory at approximately the operating point. One embodiment provides clock recovery for a received ADSL subchannel and a means to recover a 16 kHz clock for a channel control.

Abstract: A data processing system (20) having programmable chip select signal negation. A user programmable "NEGATE EARLY" value generates a chip select negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. Early negation of a chip select signal provides an efficient method of interface with slower devices while providing adding functionality to the chip select signal.

Abstract: An extensible central processing unit (CPU) (12 or 12'). By modifying the architecture of a new or prior art CPU, a new or prior art CPU can be made extensible so that new instructions can be added in a simple and cost effective manner to meet differing customer needs. The term "extensible" in regard to a CPU is used to mean that new instructions can be added to the CPU simply by adding certain designated circuitry, without the need to significantly change the existing CPU circuitry. In some embodiments, the additional designated circuitry may include control circuitry in the form of CPU control extension circuitry (52 or 152). In some embodiments, the additional circuitry may include non-control circuitry in the form of execution unit extension circuitry (153).

Abstract: A process for designing and forming a reticle (40) as well as the manufacture of a semiconductor substrate (50) using that reticle (40). The present invention places outriggers (32, 34, 36) between features (30) in both dense and semi-dense feature patterns to assist in the patterning of device features. The width of the outriggers can be changed based on pitch and location between features in a semi-dense or dense feature pattern. In one embodiment, the outriggers can be manually or automatically inserted into the layout file after the locations of the attenuating features have been determined. The outriggers are not patterned on the substrate, but assist in forming resist features of uniform width.

Abstract: An integrated circuit (10) includes a memory (20) which has a plurality of memory modes, including a high density memory mode and a high speed/reliability memory mode. The high speed/reliability memory mode may alternately be used as a high reliability memory mode. Memory (20) includes a configuration circuit (80) which selects one of the plurality of memory modes. Configuration circuit (80) provides configuration information to sense amplifier control circuit (72). Sense amplifier control circuit (72) provides control information to sense amplifiers (70) in order to place sense amplifiers (70) in one of a plurality of operating modes. In one embodiment, the plurality of operating modes of sense amplifiers (70) includes a complementary differential operating mode and a referenced differential operating mode.

Abstract: A data processing system which calculates timing delays in a circuit having a switching device (3). A computer processor (22) receives input describing a circuit and calculates the timing delays for each switching device (3) or stage. To perform each calculation the computer processor (22) models the circuit incorporating effective resistance R.sub.eff (24), Miller capacitance C.sub..mu. (7), and an associated Miller coefficient. The Miller coefficient is a defined by the behaviour of the model. The model is then reduced to a set of equations, the variables are determined, and the timing delay calculated. In one embodiment, successive stages are calculated to locate timing violations in circuit design. In alternate embodiments, models such as CRYSTAL (4) or the Sakurai model are enhanced by Miller capacitance considerations, however many other models may be used.

Abstract: A method for accessing a control register in a data processing system which ignores a first write to sensitive control bits when in a first mode, but allows subsequent writes to the sensitive control bits. When operating in a user mode, the method allows a first write to the sensitive control bits, but does not allow any subsequent writes. When a write access is made to the sensitive control bits during test mode only non-initial writes are effective. When a write access is made to the sensitive control bits during user mode only an initial write is effective. The method is effective in a data processing system having a control register write access scheme.

Abstract: A method and apparatus for efficiently performing a cache operation in a processor (70) for both flushing and non-flushing. One embodiment uses a cache flush control bit (100) in a data cache (90) to determine whether or not to ignore valid bits (130) during a pseudo least recently used (LRU) replacement algorithm. When the replacement algorithm is being used for flushing the data cache (90), the valid bits (130) are not used in order to make the algorithm more efficient. If the valid bits (130) are ignored, then the least recently used bits (120) are used to select the cache line that will be replaced. However, when the replacement algorithm is being used for a non-flushing replacement purpose, the valid bits (130) are used first, followed by the plurality of least recently used bits (120), to select the cache line that will be replaced.