Abstract: A laser method scribes graphics on materials. The method relates to the identification and understanding of a new energy measurement called energy density per unit time, and the identification and simultaneous control of the laser operating parameters which influence this energy measurement. Once a range of energy density per unit time is determined for scribing a desired graphic on a given material, the energy density per unit time can be controlled to stay within that range to achieve desired results in a repeatable fashion. In a preferred embodiment, the material is one of a group of fabric, leather and vinyl materials. In this embodiment, the energy density per unit time can be controlled to substantially avoid complete carbonization, melting and/or burnthrough of the material.

Abstract: The present invention discloses a flash memory array in which four memory cells formed on a silicon substrate having a double well structure hold a source region or a drain region in common so that the area occupied by contact holes can be minimized and integration of device can be enhanced.

Abstract: The method of forming a polycide layer in a semiconductor device is provided. The method of forming a polycide layer comprises the steps of depositing a doped polysilicon layer on a silicon substrate on which an insulating layer is formed and depositing a tungsten silicide on the doped polysilicon layer, the doped polysilicon layer comprises a lower, intermediate and upper doped polysilicon layers sequentially formed, also the intermediate polysilicon layer has a lower concentration of impurity ion than the upper and lower polysilicon layers. The impurity ions contained within the upper and lower polysilicon layers are diffused into the intermediate layer having the lowest concentration of impurity during a subsequent annealing process, therefore the impurity ions contained within the upper and lower polysilicon layers are not diffused to the junction and the tungsten silicide.

Abstract: The present invention disclosed a method of erasing a flash memory comprising the step of applying a drain bias voltage for erasing to any one of said sectors; applying a drain bias voltage for erasing to a next sector before said sector is completely erased, whereby the sectors are erased sequentially.

Abstract: The present invention discloses an erasure method which can minimize a flow of current from a drain region into a substrate due to a strong electric field formed between the drain region and the substrate when a flash memory device is erased. The first erasure operation is performed in condition that a voltage of -13V is applied to a control gate and a drain and source regions are grounded, and the second erasure operation is then performed in condition that a voltage of -13V is applied to the control gate, a voltage of 5V is applied to the drain region and the source region is floated.

Abstract: The present invention disclosed a method of reading a flash memory cell and a read voltage generating circuit which can perform a stable read operation regardless of a power supply voltage by applying a voltage of 2V to the source, a voltage of 0V to the drain, a power supply voltage Vcc to the select gate, and a clamping voltage output from the read voltage generating circuit to the control gate upon a read operation of a split gate flash memory cell.

Abstract: The present invention relates to a method of forming a contact hole of a semiconductor device, and discloses a method of forming a contact hole of a semiconductor device which can remove an oxide film formed on the bottom of the contact hole, and make the edge portions of the entrance to the contact hole and reduce the topology of the contact hole by performing high frequency plasma etching processes in two stage in which the condition of pressure and electric power are different.

Abstract: This invention relates to an erase circuit of flash memory device comprising an erase verifying block unit outputting a final loop signal when an chip erasing operation is not performed within a predetermined time, a high voltage detection unit outputting a high voltage signal in response to an inverted chip erase signal, a buffer outputting an output enable signal in response to an inverted output enable signal, a control unit outputting a first to third select address signals in response to said final loop signal, inverted high voltage signal and output enable signal, an address counter unit outputting data in response to said first to third select address signals, an output multiplexor outputting one of a sense amp output signal, hardware flag and data read from said address counter unit in response to said first to third select address signals, sense amp control signal and hardware flag signal.

Abstract: The present invention relates to a repair circuit of a flash memory cell and repair method and has excellent effects in that it can reduce the power consumption by detecting the power supply applied to the chip, latching the repaired address stored in the fuse block after the chip itself sequentially reads the fuse block, comparing the latched address with the input repair address to access the main cell and repair cell, consuming the power only while the chip reads the fuse block, and using the latched repair address at other operation, and it can reduce the area of the chip by constructing into a cell array the cells to which the repair address is to be stored and using the sense amplifier commonly.

Abstract: The present invention relates to a method of forming a tungsten plug of a semiconductor device. After forming the tungsten plug in the contact hole, a tungsten residue existed in a portion except a contact hole is oxidized by oxidation and removed. The oxidation process is performed using a chemical mixture of hydrogen peroxide and ultrapure water. A metal wiring pattern including a reflection prevention layer can also be provided on the tungsten plug prior to the residue oxidation and removal.

Abstract: The circuit for controlling a sense amplifier according to the present invention can operate plurality of sense amplifiers groups selectively by controlling a bi-directional address signal for transferring data to the output buffer, an output buffer control signal for controlling the type of the data to be outputted into 8 byte, 16 byte etc., a sense amplifier enable signal for enabling the sense amplifier, and an erasure enable signal, therefore, the present invention can minimize a number of the sense amplifier groups, thereby reducing the power consumption and implementing a low power device.

Abstract: The program circuit according to the present invention can apply a program voltage to the only memory cells which are not programmed during a re-programming operation, thus, the present invention can be prevent a lowering of reliability of the memory cell due to a continued supply of a program bias voltage.

Abstract: This invention discloses a method of forming an electrode of semiconductor device. In the present invention, an amorphous silicon film is formed on a substrate, and silicon seeds are formed on the silicon film. Thereinafter, the heat treatment is performed for growing, thereby forming an hemispherical roughness structure on surface of said charge storage electrode and increasing a surface area in unit area.

Abstract: The present invention discloses a negative voltage drive circuit which does not takes an influence from the load capacitor or the power supply voltage drive circuit according to the present invention comprises a cross pumping circuit, a pumping unit block and circuit for supplying VCC or VSS power supply voltages for the pumping unit block.

Abstract: A laser system for processing surfaces of a variety of materials. The amount of laser treatment received is controlled by a probability distribution matrix that is programmed into a control computer. In particular, the control computer can control a scanning laser beam to simulate the statistically random property of the particle distribution in a sandblasting process to generate a feathered worn look.

Abstract: The present invention discloses a plasma etching apparatus which can protect the surface of the wafer from a damage due to collisions among the etching ions and can also process a plurality of wafers only by one-time plasma generation. In the etching apparatus of the present invention, a plurality of wafers are loaded in the chamber by a plurality of wafer support members which are located vertically round the gas dispersion tube used as a cathode electrode, and magnetic field formation means are provided to form a magnetic field around each wafer.

Abstract: The present invention relates to a method of manufacturing a polysilicon film having a grain size of 0.5 .mu.m or more by forming a nucleus site of low density at low temperature of about 450.degree. C. with Si.sub.2 H.sub.6 gas, by growing an amorphous silicon film to some degree with the nucleus site, forming an amorphous silicon film of a device to a desired thickness by carrying out a main deposition process at the temperature of 500 through 600.degree. C. with SiH.sub.4 or SiH.sub.4 containing a small amount of impurity, and carrying out a heat treatment process for a long period at the temperature range of 600 through 700.degree. C. with N.sub.2 gas.

Abstract: There is disclosed a sector protecting circuit for a flash memory device. In order to prevent loss of data from a cell for sector protection, the sector protecting circuit for a flash memory device according to the present invention prevents loss of data by enabling a cell for sector protection to be erased or programmed along with a cell for normal sector.

Abstract: The present invention discloses a method of fabricating a flash memory device. In the present invention, since the dielectric film formed in the memory cell region is only exposed to the cleaning solution which is used in cleaning process preformed after removing the dielectric film formed in the low voltage transistor region, the number of damages applied to the dielectric film can be minimized, therefore, a good dielectric film can be obtained.

Abstract: A contact mask having guard ring patterns for manufacturing a semiconductor device which can prevent a lifting of a photoresist film in guard ring regions. A first guard ring pattern and a second guard ring pattern in the contact mask are formed along the perimeter portion of contact patterns in the contact mask. The first and second guard ring patterns have a plurality of discontinuous patterns, respectively. Each of the discontinuous patterns of the first guard ring pattern and each of the discontinuous patterns of the second guard ring pattern are formed in a zigzag pattern relative to each other. During the etching process using the contact mask, a photoresist pattern for the guard ring is not lifted due to an insufficient area existing between the photoresist pattern and an insulating layer in the guard ring region.