Abstract: A flash EEPROM cell according to the present invention is manufactured in accordance with the following processes: forming a oxide film on a portion of the silicon substrate by means of the LOCOS process using the patterned nitride film as an oxidation preventing layer; dry-etching a portion of the oxide film using the patterned nitride film as the etching mask; forming a tunnel oxide film, forming floating gates of a symmetric structure at the etched face; removing the patterned nitride film; forming source and drain regions by means of the self-aligned ion implantation method using the residual oxide film remaining below the patterned nitride film and the floating gates; removing the residual oxide film; forming a select channel region at this portion by means of the ion implantation process for controlling a threshold voltage; and then forming an interpoly oxide film and a control gate by means of the common processes.

Abstract: This invention relates to a test pattern structure comprising a test pattern structure for endurance test of a flash memory device comprising: at least three active regions formed on a semiconductor substrate, each active region being isolated by a field oxide film; a common drain region formed on each active region, respectively; source regions formed on left and right sides of the common drain region in each active region, respectively; a first common floating gate formed along left side of each common drain region; a second common floating gate formed along right side of each common drain region; a control gate overlapped with the first and second floating gates, respectively and connected from each other at both ends of the first and second floating gates; a select gate formed over the common drain region, the source regions and the control gate in each active region, respectively; and metal wires connected to the common drain region, the source regions and the control gate in each active region, respecti

Abstract: A memory cell array with an active region which has first portions and fifth portions which are at both ends thereof and a third portion which is the middle portion thereof. The first, third and fifth portions are parallel to each other with a certain spacing. The first and third portions are interconnected by a second portion sloped toward a side of the third portion. The third portion and fifth portions are interconnected by a fourth portion sloped upward from the other side of the third portion. Source regions are formed in the first and fifth portions and fifth portion of the active region. A drain region is formed in the third portion of the active region. Channel regions are formed in the second portion and fourth portion of the active region. Floating gates are disposed over each of the channel regions. A pair of control gates is disposed over the floating gates.

Abstract: The flash EEPROM cell of split-gate type according to the present invention can prevent the degradation of the tunnel oxide film of the cell due to the band-to-band tunneling and the secondary hot carrier which are generated by a high electric field formed at the overlap region between the junction region and the gate electrode when programming and erasure operations are performed by a high voltage to the structure in which the tunneling region is separated from the channel with a thick insulation film.

Abstract: The present invention discloses a method of planarizing an insulating layer of a semiconductor device. The method of the present invention comprises a first polishing step for rotating the platen and the rotating carrier holding the wafer contacted with the polishing pad secured to the platen, applying a nitrogen (N.sub.2) gas to the rear surface of the wafer to contact a surface of the wafer with the polishing pad, and applying force to the wafer through the rotating carrier to press the wafer against the polishing pad. Then, a second polishing step for increasing a speed of revolution of the platen and the rotating carrier and decreasing the force applied to the wafer is performed.

Abstract: The flash EEPROM cell of split-gate type according to the present invention can prevent the degradation of the tunnel oxide film of the cell due to the band-to-band tunneling and the secondary hot carrier which are generated by a high electric field formed at the overlap region between the junction region and the gate electrode when programming and erasure operations are performed by a high voltage to the structure in which the tunneling region is separated from the channel with a thick insulation film.

Abstract: The repair fuse circuit of the present invention comprises a power-on reset circuit to generate first and second control signals in response to a reset pulse which is generated upon power-on; a delay circuit to generate second and fourth control signals which are delayed according to the first control signal; a gate voltage control circuit to generate a fifth control signal which is delayed according to the third control signal; a reference voltage generating circuit to generate a reference voltage in response to the fourth control signal; a fuse cell sensing and latching circuit to latch a data stored on a fuse cell in response to the fifth control signal; and an address compare circuit to generate a redundant address by comparing an output of the fuse cell sensing and latching circuit with a normal address.

Abstract: The mask for checking lens distortion comprises a plurality of mother verniers formed at each portion of the quartz and a plurality of the daughter verniers spaced from each of the plurality of the mother verniers.

Abstract: A negative voltage drive circuit according to the present invention comprises a switching means coupled between an input terminal and an output terminal; a cross latch pumping means for controlling the switching means in response to first and second clock signals and for maintaining the lower output voltage than that of said charge pump; and a capacitor which starts pumping operation according to the first clock signal when the output terminal is isolated to the input terminal.

Abstract: The present invention discloses a method of forming a plug in a semiconductor device. Metals having different properties are employed to induce the growth of the metals in fixed direction within the contact hole so as to prevent an over-etching which is generated due to a difference of density depending on the growth direction of the metal in the contact hole. Upon a full-surface etching process for forming a plug, the step difference generating on top of the contact hole can be minimized, thereby improving the step coverage of the metal during a subsequent metalization process and increasing the electrical characteristic and reliability of the device.

Abstract: A flash memory device according to this invention comprises a main cell array block consisted of a main cell array and a dummy cell array; a first and second multiplex blocks to which data of the main cell array are input; a first and second column multiplex blocks to which data of the main cell array block are input; a first and second repair multiplexers to control the first and second multiplex blocks; a third to fifth repair multiplexers to control the first and second column multiplex blocks; a first to fifth decoders to access said main cell array of the cell array block according to an address input; a sixth and seventh decoders to access repair cell array of the cell array block according to the address input; and a redundancy fuse block comparing the inputted address with repair address and determining whether repair be done or not.

Abstract: The present invention relates to a test pattern group and a method for measuring an insulation film thickness utilizing the same, and to the test pattern group comprising at least 3 (three) test patterns having a construction of a capacitor and a method for more precisely measuring the insulation film thickness utilizing the test pattern group, in a method for electrically measuring a capacitance of the insulation film applied to a semiconductor device and converting the measured capacitance to a thickness of the insulating film.

Abstract: The present invention relates to the charge pump circuit and, more particularly to the charge pump circuit which can decrease the time period of voltage rise of the charge pump circuit by making the charge pumping voltage outputted from the output stage of the pump circuit section to be satisfactorily supplied to the load section, by making the rate of the gate voltage rise of the voltage drop transistor to be higher than the rate of drain voltage rise.

Abstract: This invention discloses a method of manufacturing a semiconductor device, especially a method of forming field isolation, in which a portion of an active region around a field oxide film is highly-doped with the same type impurities as channel-stop impurity ions so that it changes a low-doped channel-stop region which results from a high temperature of field oxidation to a high-doped channel-stop region to prevent field inversion in device operation.

Abstract: The present invention relates to memory cell array, each floating gate of each memory cell is placed between each drain region and each source region so that four memory cells hold single source region or single drain region in common.