Abstract: An unlicensed wireless service is adapted to generate the interface protocols of a licensed wireless service to provide transparent transition of communication sessions between a licensed wireless service and an unlicensed wireless service. In one embodiment, a mobile station includes level 1, level 2, and level 3 protocols for licensed wireless service and an unlicensed wireless service. An indoor base station and indoor network controller provide protocol conversion for the unlicensed wireless service into a standard base station controller interface of the licensed wireless service.
Type:
Grant
Filed:
October 17, 2003
Date of Patent:
October 24, 2006
Assignee:
Kineto Wireless, Inc.
Inventors:
Michael D. Gallagher, Jahangir Mohammed, Joseph G. Baranowski, Jianxiong Shi, Milan Markovic, Thomas G. Elam, Kenneth M. Kolderup, Madhu C. Shekhar, Mark Powell
Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes an interconnect circuit having a first set of input terminals and a set of output terminals. The interconnect circuit has several connection schemes for connecting the first input set to the output set. The IC also has a second set of input terminals for carrying a set of input signals, where at least several of the second set of input terminals overlap at least a plurality of the first set of input terminals. The IC further has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set. The interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes.
Abstract: Some embodiments of the invention provide a method of routing nets in a multi-layer integrated-circuit (“IC”) layout. For each particular net in a set of nets, the method specifies different spacing constraints for routing the particular net in different directions on the same layer. It then defines a particular route for each particular net in the set of nets, where the spacing between at least one particular route and an item adjacent to the route in the layout is different in the different directions on the same layer.
Abstract: The invention is directed towards methods and apparatuses for archiving and unarchiving objects. Some embodiments of the invention archive and unarchive objects that have global and user settings in multi-user environments. To archive objects, these embodiments identify which object settings are global settings and which settings are user settings. They store the global settings in an archive, and then store the user settings in another archive. To unarchive each object, some embodiments identify the object's settings in one or both archives. These embodiments instantiate the object, and retrieve its settings from the data archives and use the retrieved settings to define the values of the settings of the instantiated object. Some embodiments use key-value coding techniques to retrieve values and load values in an object. Key-value coding allows an archiving or unarchiving process to retrieve and load setting values for an object by using the setting names.
Abstract: The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.
Type:
Grant
Filed:
October 10, 2003
Date of Patent:
October 3, 2006
Assignee:
Cadence Design Systems, Inc.
Inventors:
Steven Teig, Raghu Chalasani, Akira Fujimura
Abstract: Some embodiments of the invention provide a method of decomposing a design layout. The method decomposes the layout into a tessellated graph with several edges. It then computes the capacity of the edges based on a interconnect line model that is used to connect elements in the design layout. The layout has two orthogonal coordinate axes. At least one interconnect line specified by the model is neither parallel nor perpendicular to the coordinate axes. Also, in some embodiments, some of the edges are neither parallel nor perpendicular to the coordinate axes.
Abstract: Some embodiments of the invention provide configurable integrated circuit (IC) that has a first interface rate for exchanging signals with a circuit outside of the configurable IC. The configurable IC has an array of configurable circuits. The array includes several configurable logic and interconnect circuits. Each configurable logic circuit can configurably perform a set of functions. The configurable interconnect circuits can configurably couple the logic circuits. At least several of the configurable circuits can be reconfigured faster than the first rate.
Type:
Grant
Filed:
June 30, 2004
Date of Patent:
September 19, 2006
Inventors:
Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
Abstract: An unlicensed wireless service is adapted to generate the interface protocols of a licensed wireless service to provide transparent transition of communication sessions between a licensed wireless service and an unlicensed wireless service. In one embodiment, a mobile station includes level 1, level 2, and level 3 protocols for licensed wireless service and an unlicensed wireless service. An indoor base station and indoor network controller provide protocol conversion for the unlicensed wireless service into a standard base station controller interface of the licensed wireless service.
Type:
Grant
Filed:
September 14, 2005
Date of Patent:
September 12, 2006
Assignee:
Kineto, Wireless, Inc.
Inventors:
Michael D. Gallagher, Jahangir Mohammed, Joseph G. Baranowski, Jianxiong Shi, Milan Markovic, Thomas G. Elam, Kenneth M. Kolderup, Madhu C. Shekhar, Mark Powell
Abstract: One embodiment of the invention is a method of specifying routes for a group of nets. The method identifies different routing solutions for the group of nets. It then selects the best routing solution.
Abstract: An inductive (“L”)-capacitive (“C”) filter bank has application for use in a television receiver. The LC filter includes inductors configured in at least one inductive (“L”) bank, and capacitors configured in at least one capacitive (“C”) bank. The inductors and capacitors are selectively enabled so as to configure an LC filter with at least one inductor from the L bank and at least one capacitor from the C bank. A combination of inductors and capacitors are selected through the semiconductor switches so as to maximize a Q factor for the LC filter.
Abstract: A system for using machine learning based upon Bayesian inference using a hybrid Monte Carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Then, for each of the smaller simpler extraction problems, complex mathematical models are created using machine learning techniques.
Abstract: The present invention discloses a method for quickly and easily authenticating large computer program. The system operates by first sealing the computer program with digital signature in an incremental manner. Specifically, the computer program is divided into a set of pages and a hash value is calculated for each page. The set of hash values is formed into a hash value array and then the hash value array is then sealed with a digital signature. The computer program is then distributed along with the hash value array and the digital signature. To authenticate the computer program, a recipient first verifies the authenticity of the hash value array with the digital signature and a public key. Once the hash value array has been authenticated, the recipient can then verify the authenticity of each page of the computer program by calculating a hash of a page to be loaded and then comparing with an associated hash value in the authenticated hash value array.
Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.
Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.
Abstract: Some embodiments of the invention provide an improved spectrometer that measures light emissions and/or reflection from a non-solid material that flows through a system of pipes. This spectrometer is designed to fit into a standard pipe system. The material flows past a distal end of the spectrometer that is inserted in the pipe system. The spectrometer has the ability to project light onto the material and collect a resulting light from the material through the distal end as the material flows past this end.
Type:
Grant
Filed:
October 15, 2003
Date of Patent:
August 29, 2006
Assignee:
Turner Designs, Inc.
Inventors:
James Crawford, David Doting, Robert Ellison, Sang Hoang, Steven Monsef, Frank J. Szczurko, Jr.
Abstract: Some embodiments provide a method of routing nets within a region of an integrated-circuit (“IC”) layout. The method uses a first set of lines to partition the IC region into a plurality of sub-regions. In addition, the method uses a second set of lines to measure congestion of routes for the nets within the IC region. According to this method, at least some of the lines in the second set are different from the lines in the first set.
Abstract: Some embodiments of the invention provide a method of routing nets in a multi-layer integrated-circuit (“IC”) layout. For a particular net, the method specifies widths for routing the particular net in different directions on the same layer. It then defines a particular route for the particular net, where the route has different widths in the different directions on the same layer.
Abstract: Some embodiments of the invention provide a method of identifying a group of routes for a set of nets. The group of routes includes one route for each net in the set of nets. The method identifies a set of routes for each net. It then iteratively selects one identified route for each net. During each iteration, the method selects the identified route that least increases a tracking cost that accounts for each of the previously selected routes.
Abstract: The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.
Abstract: A discrete inductive-capacitive (LC) filter selects between at least two inductor banks to tune the LC filter. The filter receives an input signal that includes one or more bands of frequencies. A control signal selects a band of frequencies for processing. A first inductor bank is selected to filter a first band of frequencies, and a second inductor bank is selected to filter a second band of frequencies. A switch circuit couples the input signal to either the first inductor bank or the second inductor bank. The switch circuit selects the first inductor bank if the first band of frequencies is selected, and selects the second inductor bank if the second band of frequencies is selected. The switch circuit electrically isolates the switching of the input signal to the first and the second inductor banks, so as to enhance the Q factor of the LC filter. Circuit and techniques are disclosed to reduce parasitic capacitance in a capacitive bank that employs MOS transistors.