Abstract: A method and apparatus for variable accuracy inter-picture timing specification for digital video encoding is disclosed. Specifically, the present invention discloses a system that allows the relative timing of nearby video pictures to be encoded in a very efficient manner. In one embodiment, the display time difference between a current video picture and a nearby video picture is determined. The display time difference is then encoded into a digital representation of the video picture. In a preferred embodiment, the nearby video picture is the most recently transmitted stored picture. For coding efficiency, the display time difference may be encoded using a variable length coding system or arithmetic coding. In an alternate embodiment, the display time difference is encoded as a power of two to reduce the number of bits transmitted.

Abstract: A method of extracting capacitance for a first wire segment is disclosed. The method approximates a non orthogonal first section of interconnect wiring containing the first wire segment by using an orthogonal second section of interconnect wiring. The method determines an estimated capacitance of the non orthogonal first section of interconnect wiring by using the orthogonal second section of interconnect wiring. The method adds a correction factor to the estimated capacitance to generate a modeled capacitance value for the non orthogonal first section of interconnect wiring.

Abstract: A method for defining and producing a power grid structure of an IC having diagonal power and ground stripes. Stripes are placed in a 45° or 135° diagonal direction in relation to an IC layout's x-coordinate axis so that the stripes will be placed in a 45° or 135° diagonal direction, respectively, in relation to the bottom boundary of the resulting IC. The diagonal power and ground stripes are beneficial to diagonal signal wiring. The stripes may be placed across one layer of the IC or across more than one layer of the IC. The diagonal power stripes may have varying widths and/or varying spacing widths on a layer of the IC. The diagonal ground stripes may have varying widths and/or varying spacing widths on a layer of the IC.

Abstract: A method for modifying an IC layout using a library of pretabulated models, each model containing an environment with a feature, one or more geometries, and a modification to the feature that us calculated to produce a satisfactory feature on a wafer. The model may also contain a simulation of the environment reflecting no processing variations and/or a re-simulation of the environment reflecting one or more processing variations. The model may also contain data describing an electrical characteristic of the environment as a function of one or more process variations and/or describing an adjustment equation that uses geometry coverage percentages of particular areas in the layout to determine an adjustment to the modification. In some embodiments, and upper layer for an upper layer of an IC are modified using information (such as a density map) relating to a lower layout for a lower layer of the IC.

Abstract: For a placer that partitions a region of a circuit layout into a plurality of sub-regions, some embodiments provide a method of computing placement costs. For a set of sub-regions, the method identifies a connection graph that connects the set of sub-regions. The connection graph has at least one edge that is at least partially diagonal. The method then identifies a placement cost from an attribute of the connection graph.

Abstract: For a router that allows routing in at least one non-Manhattan direction, some embodiments of the invention provide a method of computing a capacity for non-Manhattan routing in a region. The method identifies a polygon about the region, where the polygon has at least one side that is not aligned with either Manhattan direction. It then identifies a set of potential obstacles within the polygon. The method then calculates the capacity of the region for non-Manhattan routing, based on the identified set of potential obstacles.

Abstract: Some embodiments of the invention provide a method of specifying routes in a design layout, where each route has a set of segments and each segment has a shape. The method receives a route, and for each segment of the received route, identifies n half planes that when intersected provide the shape of the segment. In some embodiments, n is an integer greater than 4. Some embodiments provide a method of generating a representation of a route formed by several adjoining polygons. For each polygon, this method (1) identifies a direction for the polygon, (2) defines a segment along the identified direction, where the segment has a starting point and an ending point, and (3) identifies more than four values that specify more than four half planes in conjunction with the starting and ending points of the segment, where the intersection of the specified half planes provides the shape of the polygon. Some embodiments provide a design layout that has several routes that are each represented by a set of segments.

Abstract: Some embodiments of the invention provide a method of identifying a via between at least two layers of a multi-layer design layout. The method identifies a region within which the via should be located. It then formulates an optimization problem for identifying a location of the via in the region. It then solves the optimization problem to find an optimized location for the via.

Abstract: A record management system is provided for generating a multi-dimensional view for different measures. A set of records is retrieved in response to a set of queries. The records include dimension values and measure values, which are associated with the measures. The set of records is maintained in a master table. The record management system generates a record structure foundation, including a query map and a master table index. The record management system then employs the record structure foundation to generate a multi-dimensional layout mapping for the measures that are to be represented in the view. The record structure foundation and measure values in the master table are used to convert the layout mapping into the desired multi-dimensional view.

Abstract: An analog finite impulse response (“FIR”) filter generates a continuous time output using a chain of tunable delay elements. The tunable delay elements generate a time delay in an input signal. A calibration circuit, consisting of a control loop, tunes the delay elements to provide precision in the time delay response of the delay elements. The control loop generates a delay adjustment, based on the period of reference signals, and the phase adjustment is used to tune the parameters of the delay elements. The tunable delay elements may comprise any combination of transmission lines, lumped elements and semi-lumped elements.

Abstract: Some embodiments provide a hierarchical routing method that uses diagonal routes. This method routes a net within a particular region of an integrated circuit (“IC”) layout. This net includes several pins in the region. The method initially partitions the particular IC region into a first set of sub-regions. It then identifies a first route that connects a group of first-set sub-regions that contain the net's pins. The identified first route has an edge that is at least partially diagonal. The method next partitions the first-set sub-regions into a second set of smaller sub-regions. It then propagates the first route into the second-set sub-regions.

Abstract: Some embodiments of the invention provide a method for identifying a path between a set of source states and a set of target states in a space with more than two dimensions. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. At least some of the states are non-zero dimensional states. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method specifies at least one path that starts from one state. It then iteratively specifies new paths by expanding previously specified paths to other states in the space until identifying a path that connects the source and target states. At least one of the expansions of a previously specified path includes an expansion in more than two dimensions of the space.

Abstract: The invention is directed towards a method and apparatus for a portable gaming machine. The method activates several bingo games that are stored in the portable gaming machine. The activation makes the bingo games available to a bingo player for playing. The bingo player is presented with an option to switch from a first bingo game to a second bingo game while retaining numbers entered by the bingo player in the first bingo game. The method also records every keystroke entered by a bingo player for each game. These keystrokes can be displayed in an expeditious manner to a gaming official upon entering of a password.

Abstract: Some embodiments provide an analytical placement method that considers diagonal wiring. This method formulates an objective function that accounts for the use of diagonal wiring during routing. Some embodiments use horizontal, vertical, and ±45° diagonal lines.

Abstract: Some embodiments of the invention provide a method of specifying a cost function that represents the estimated distance between an external state and a set of states in a multi-state space that represents a region of a design layout. The method identifies a first polygon that encloses the set of states. It then identifies vectors to project from the vertices of the first polygon. Based on the projected vectors, the method specifies a first cost function. The method also identifies a second polygon that encloses the set of states. It also identifies vectors to project from the vertices of the second polygon. Based on the projected vectors, the method specifies a second cost function. The method then derives a third cost function from the specified cost functions.

Abstract: Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the delay cost of a placement configuration by accounting for the potential use of diagonal wiring in the layout. Some of these embodiments derive the delay cost from an estimate of the wirelength needed to route the nets in the region.

Abstract: A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. The training sets are then used to train the models.

Abstract: Some embodiments provide a method of computing the estimated distance between an external state and a set of states in a multi-state space that represents a region of a design layout. The method identifies a polygon that encloses the set of states. It then identifies vectors to project from the vertices of the polygon based on a model that allows penalizes measurements in certain directions more than other directions. Based on the projected vectors, the method then identifies the estimated distance.

Abstract: A technique for generating cross-references among categories in a knowledge base extracts a plurality of themes from a corpus of documents. A theme identifies subject matter contained in a corresponding document. A plurality of scores are generated such that each score identifies a relative theme strength among theme pairs of the themes extracted from the documents. In general, a theme strength reflects the amount of subject matter contained in a document for a corresponding theme relative to other themes in the document. Thereafter, the most related theme pairs are selected as indicated by the scores. Category pairs of the knowledge base are then selected by mapping the themes of the selected theme pairs to corresponding categories of the knowledge base. A cross-reference between categories of the category pairs in the knowledge base is generated so as to identify an association between the category pairs.