Patents Represented by Attorney, Agent or Law Firm Stephen A. Gratton
  • Patent number: 7708494
    Abstract: A water diversion system includes a hydraulic chute and a chute screen assembly in the hydraulic chute having a wedge wire screen. The water diversion system also includes at least one collection chamber located below the screen configured to collect filtered diversion water which has passed through the screen. The hydraulic chute includes a base, a crest, a sloped accelerator, and an abrupt drop with an adjustable lip, which forms a hydraulic formation in a downstream pool. The hydraulic chute can also include sloped sidewalls, which constrict the flow of water and form fish passage zones. In addition, the chute screen assembly can include a modular panel configured to facilitate construction, maintenance and replacement of the wedge wire screen.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: May 4, 2010
    Assignee: McLaughlin Consulting Company
    Inventor: Richard Evan McLaughlin
  • Patent number: 7682962
    Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: March 23, 2010
    Assignee: Micron Technology, Inc.
    Inventor: David R. Hembree
  • Patent number: 7659612
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: February 9, 2010
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 7589406
    Abstract: A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive members bonded to corresponding conductive openings on the semiconductor substrates. The component can also include terminal contacts on the carrier in electrical communication with the conductive members, and an outer member for protecting the semiconductor substrates. A method for fabricating the component includes the steps of providing the carrier with the conductive members, and providing the semiconductor substrates with the conductive openings. The method also includes the step of aligning and placing the conductive openings on the conductive members, and then bonding the conductive members to the conductive openings.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: September 15, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Alan G. Wood
  • Patent number: 7579267
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: August 25, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, David R. Hembree
  • Patent number: 7550315
    Abstract: A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate.
    Type: Grant
    Filed: July 22, 2007
    Date of Patent: June 23, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Victor Tan Cher ′Khng, Lee Kian Chai
  • Patent number: 7547385
    Abstract: A method for producing a supercritical cryogenic fuel (SCCF) includes dissolving a hydrogen gas in fuel value proportions into a supercritical hydrocarbon fluid. The method is performed by placing a hydrogen gas and a hydrocarbon fluid at a pressure greater than the critical pressure of the hydrocarbon, placing the hydrogen gas and the hydrocarbon fluid at a temperature below or approximately equal to the critical temperature of the hydrocarbon forming the supercritical hydrocarbon fluid, and then mixing to dissolve the hydrogen gas into the supercritical hydrocarbon fluid. A system for performing the method includes a vortex mixer configured to turbulently mix the hydrogen gas and the supercritical hydrocarbon fluid. The supercritical cryogenic fuel (SCCF) produced by the method and the system includes the supercritical hydrocarbon fluid with a selected mole fraction of the hydrogen gas dissolved therein.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: June 16, 2009
    Assignee: Eden Innovations Ltd.
    Inventors: Gregory J. Egan, Robert Rudland
  • Patent number: 7539513
    Abstract: A portable phone includes a handset and a data projection system configured to form a visual image of data, such as caller waiting ID data, on a viewing surface viewable by a user during a two way conversation. The handset also includes a speaker, a microphone, conventional phone circuitry and a keyboard. The data projection system is configured to receive signals from the phone circuitry, to generate a pattern representative of the data, to process the pattern into a mirror image of the visual image, and to project the mirror image from a bottom end surface of the handset. The projection system includes an electro optic system for generating the pattern, and an optics system for projecting the mirror image onto the viewing surface.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: May 26, 2009
    Assignee: National Telephone Products, Inc.
    Inventors: David A. Cathey, Jr., Steven Howell, James Cathey
  • Patent number: 7538413
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact on a circuit side thereof in electrical communication with an integrated circuit, and a through interconnect in physical and electrical contact with the substrate contact configured to provide a signal path to a back side of the semiconductor substrate. The through interconnect includes an opening in the semiconductor substrate aligned with the substrate contact, and a projection on an interposer substrate (or alternately on a second semiconductor substrate) configured for mating physical engagement with the opening in the semiconductor substrate. The projection can also include a conductive via configured for electrical contact with a backside of the substrate contact and with a terminal contact for the component.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 26, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Warren M. Farnworth, David R. Hembree
  • Patent number: 7537966
    Abstract: A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the substrate in a BOC configuration, wire bonding wires through the opening to the conductors and the bumps, and forming a die encapsulant on the die.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: May 26, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Mike Connell, Tongbi Jiang
  • Patent number: 7531443
    Abstract: A method for fabricating semiconductor components includes the step of providing a semiconductor substrate having a circuit side, a back side, a plurality of integrated circuits on the circuit side, and a plurality of substrate contacts on the circuit side in electrical communication with the integrated circuits. The method also includes the steps of forming vias from the back side to the substrate contacts, forming a conductive layer in the vias and on the back side in electrical contact with the substrate contacts; and forming the conductive layer on the back side into a plurality of conductors in electrical communication with the substrate contacts. The semiconductor component includes the semiconductor substrate, the through interconnects and the redistribution conductors. Each through interconnect includes a via aligned with a substrate contact, and a conductive layer at least partially lining the via in physical and electrical contact with the substrate contact.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: May 12, 2009
    Assignee: Micron Technology, Inc.
    Inventor: David S. Pratt
  • Patent number: 7497191
    Abstract: A system for producing, dispensing, using and monitoring a hydrogen enriched fuel includes a producing system configured to produce the hydrogen enriched fuel, a vehicle having an engine configured to use the hydrogen enriched fuel, and a dispensing system configured to store and dispense the hydrogen enriched fuel into the vehicle. The system also includes a fuel delivery system on the vehicle configured to deliver the hydrogen enriched fuel to the engine, and a control system configured to control the producing system and to monitor the use of the hydrogen enriched fuel by the vehicle. A method includes the steps of producing hydrogen gas and a hydrocarbon fuel, blending the hydrogen gas and the hydrocarbon fuel into the hydrogen enriched fuel, using the hydrogen enriched fuel in the engine, and tracking emissions during the producing step and during the using step.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: March 3, 2009
    Assignee: Eden Innovations Ltd.
    Inventors: Justin Fulton, Roger W. Marmaro, Gregory J. Egan
  • Patent number: 7498675
    Abstract: A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: March 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, William M. Hiatt, James M. Wark, David R. Hembree, Kyle K. Kirby, Pete A. Benson
  • Patent number: 7488359
    Abstract: Apparatus and processes are provided for the generation of hydrogen which employ a reformer and water gas shift reactor. The apparatus and processes respond quickly to changes in hydrogen generation. The reformate in a region between the reformer and prior to exiting the water gas shift reactor is cooled by indirect heat exchange with water whereby substantially all the water is vaporized to steam, the steam is separated from liquid water and then introduced into the reformate.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: February 10, 2009
    Assignee: HyRadix, Inc.
    Inventor: Robert J. Sanger
  • Patent number: 7482833
    Abstract: A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed such that when a leg is not being utilized, the tuning transistors in the unused leg are placed in a tri-state. For example, during an ODT mode of the output driver, the tuning transistors in the non-ODT legs are tri-stated. During a READ mode of the output driver, the tuning transistors in the ODT legs are tri-stated. During a HiZ mode of the output driver, the tuning transistors in both legs are tri-stated. Tri-stating the tuning transistors in the unused output driver legs can reduce DQ pin capacitance by a total of approximately (Cgd+Cgs+Cgb).
    Type: Grant
    Filed: April 21, 2007
    Date of Patent: January 27, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Raghukiran Sreeramaneni
  • Patent number: 7482702
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: January 27, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 7479413
    Abstract: A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: January 20, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Mike Connell, Tongbi Jiang
  • Patent number: 7473582
    Abstract: A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In addition, the pin contacts are formed by terminal portions of the conductive members. The fabrication method includes the steps of forming the openings and the conductive members, and then thinning and etching the die to form the pin contacts. An alternate embodiment female component includes female conductive members configured to physically and electrically engage pin contacts on a mating component of a stacked assembly.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: January 6, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Trung Tri Doan
  • Patent number: 7459393
    Abstract: A method for fabricating a semiconductor component includes the steps of providing a substrate having a contact on a circuit side thereof, forming an opening from a backside of the substrate to the contact, forming a conductive via in the opening in electrical contact with a surface of the contact, and forming a second contact on the back side in electrical communication with the conductive via. The method can also include the steps of thinning the substrate from the backside, forming insulating layers on the circuit side and the backside, and forming a conductor and terminal contact on the circuit side in electrical communication with the conductive via. A semiconductor component includes the contact on the circuit side, the conductive via in electrical contact with the contact, and the second contact on the backside in electrical communication with the conductive via. The semiconductor component can also include the insulating layers, the conductor and the terminal contact.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: December 2, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, William M. Hiatt, James M. Wark, David R. Hembree, Kyle K. Kirby, Pete A. Benson
  • Patent number: 7459778
    Abstract: A leadframe for semiconductor components includes leadfingers, interconnect bonding sites for wire bonding to a semiconductor die, terminal bonding sites for terminal contacts for the component in an area array, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe relative to the bus bars such that shorting to the bus bars by wire interconnects is eliminated.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: December 2, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Dalson Ye Seng Kim, Jeffrey Toh Tuck Fook, Lee Choon Kuan