Abstract: It is shown a low noise amplifier comprising a first circuit block suitable for converting a first amplifier input voltage signal into current, a second circuit block adapted to divide the current coming from said first block, said second block being controlled by a second voltage signal, said first and second blocks conferring a variable voltage gain to the amplifier. The amplifier comprises at least one first and at least one second resistors and a feedback network, said at least one first resistor connected with one first output terminal of said second block and with a supply voltage, and said at least one second resistor being connected between said at least one first and at least one second output terminals of said second block, and said feedback network being coupled with said at least one first terminal and with said first circuit block, and said at least one second terminal being coupled with at least one output terminal of said low noise amplifier.

Abstract: A method is provided for packaging an integrated circuit chip that has a front face with sensors located in a central region and electrical connection areas located in a region that lies between at least one edge of the chip and the central region. According to the method, a rear face of the chip is cemented to a front face of a substrate that includes through-holes, with the rear face of the substrate including electrical connection areas that pass in front of the through-holes such that the through-holes are located laterally with respect to the edge of the chip. The electrical connection areas on the front face of the chip are connected to the electrical connection areas on the substrate through the through-holes, and the chip is embedded in an optically transparent encapsulating material so as to form an encapsulating block on the same side as the front face of the substrate. The substrate is cut around the encapsulating block, following the perimeter of the encapsulating block.

Abstract: A system for making presentations to audience clients in a computer network. The presentation is made by a presenter client via a Web server connected to one or more audience client units. Each audience client unit has a browser for linking to the network. The system comprises a receiver for receiving and processing page requests from at least one presenter client; a transmitter for transmitting requested pages to the presenter client; and a server siphon for intercepting composed pages and sending copies of each composed page to at least one connected audience client.

Abstract: Several peripheral entities, each of which is clocked by its own internal clock signal, can access a memory that is a single-access memory. A priority entity is defined from among the peripheral entities, and the other entities are defined as auxiliary entities. A repetitive time frame is formulated so as to be regulated by the internal clock signal of the priority entity. This time frame is subdivided into several groups of windows that are allocated to the peripheral entities. Each peripheral entity can access the memory only during the windows that are allocated to that entity.

Abstract: A machine for testing electronic components or chips formed in a wafer (3) and each comprising a multiplicity of electrical connection pads formed on the surface of the wafer, which machine includes a test head (5) having a multiplicity of electrical connection test prods (11) and a mechanism for moving the wafer to be tested with respect to the head so as to bring the ends of the test prods into contact with the pads of each chip, in succession. The test head (5) carries heating and temperature-regulating elements (18) thermally coupled to the electrical connection test prods (11). Preferably, the test head (5) includes a metal block (16) thermally coupled to the electrical connection test prods (11). The heating and temperature-regulating elements (18) are thermally coupled to the metal block.

Abstract: A multiplication circuit with an accumulator is provided. The multiplication circuit includes first latch circuits, second latch circuits, and elementary adders that are cascade-coupled to one another in series through the first latch circuits. Each of the adders has its carry output coupled to one of its inputs through one of the second latch circuits. Additionally, cancellation circuitry cancels the contents of each of the second latch circuits at least during selected multiplication operations so as to carry out multiplication operations in a Galois field. In some preferred embodiments, the cancellation circuitry includes a logic gate that receives a selection signal indicating the mode of operation, and the logic gate sets and holds the second latch circuits at zero when the selection signal indicates that the multiplication operation is to be done in a Galois field.

Abstract: A broadcast datastream is received, and audio identifying information is generated for audio content from the broadcast datastream. It is determined whether the audio identifying information generated for the broadcast audio content matches audio identifying information in an audio content database. In one preferred embodiment, the audio identifying information is an audio feature signature that is based on audio content. Also provided is a system for monitoring broadcast audio content.

Abstract: A method for estimating the frequency error of a demodulator for restoring two binary signals carried on two carriers of same frequency but in phase quadrature, including the steps of forming vectors having as components the successive couples of values of the two binary signals; applying to each vector a transform which multiplies by four its angle at least when it is equal to a multiple of &pgr;/4 and which substantially preserves its module; and calculating the average of the transformed vectors. The frequency error is obtained as being the derivative of the angle of the average vector.

Abstract: This invention provides a defragmentation utility that works on-line in parallel with other file system activities. Thus, it avoids making the file system unavailable for periods of time which would, if not for this invention, slow down data communication exchange and the execution of other tasks dependent upon the data. In particular, this invention, steps through all of the valid inodes finding each of the fragments. The defragmentation engine decides which fragments must remain in their current location and which fragments should migrate to another disk block sub-block location. Since the data blocks span across multiple disks, for each valid disk of the file system a set of disk blocks are constructed that are chosen to be filled, herein called plates. When the plates become full or reach a certain fullness, they are removed from the set and replaced by other disk blocks. When a disk block is removed from the plate set, it is moved to a “done” list as it is considered “full”.

Abstract: The invention relates to a MOS transistors substitutive circuit having a transformer/data interface function, in particular for ISDN networks, comprising first (11a) and second (11b) power supply/transmitter blocks, the first power supply/transmitter block (11a) being connected between a voltage reference (V) and a first data interface (RX), and the second power supply/transmitter block (11b) being connected between a ground potential reference (GND) and a second data interface (TX), both power supply/transmitter blocks being connected to a supply voltage reference (VDD). The MOS transistors substitutive circuit according to the invention comprises first (12) and second (12′) MOS transistor pairs connected to the voltage reference (V), the MOS transistors being diode configured and held in their saturation range, so as to have a high A.C. impedance and virtually zero D.C. impedance, thereby minimizing power dissipation through the substitutive circuit.

Abstract: A current generator with thermal protection has an input terminal and an output terminal. The current generator includes a voltage generator, first and second controlled switches, a temperature sensor, and a control circuit. The first controlled switch has a control terminal applied to the voltage generator, a first terminal connected to the input terminal, and a second terminal connected to a resistance. The second controlled switch has a control terminal coupled to the voltage generator, a first terminal connected to the resistance, and a second terminal connected to the output terminal. The temperature sensor of the current generator measures the temperature of the generator, and the control circuit controls the second controlled switch so as to open the second controlled switch when the temperature of the current generator overcomes a preset temperature.

Abstract: A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configuration. The non-modifiable first circuitry selectively imposes one of at least a first potential and a second potential on the configuration node prior to configuration, and the modifiable second circuitry allows modification of the potential imposed on the configuration node by the non-modifiable first circuitry. In a preferred embodiment, the modifiable second circuitry includes at least one fuse that is in an intact state before configuration and that can be changed to a destroyed state after configuration. This enables a reduction in the number of fuses that have to be destroyed during the configuration of the circuit. Also provided is an information processing system that includes at least one configurable electronic circuit having configuration nodes.

Abstract: A storage device is provided. The storage device includes at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. In a preferred embodiment, a control circuit is coupled to the address bus, with the control circuit including address registers for storing as many address pointers as the number of k-bit shift registers.

Abstract: A semiconductor circuit that includes components and registration features that are electrically isolated from the components. The registration features form projecting parts that are uniformly distributed in the form of a matrix over at least part of the external surface of the circuit so as to define adjacent registration areas. In a preferred embodiment, the semiconductor circuit also includes metal registration features that are produced in at least one metallization level of the circuit. Also provided is a method of adjusting a tool so as to put it into a particular position with respect to the surface of a semiconductor circuit that has registration features defining adjacent registration areas. According to the method, an at least partial topographic record of the registration features on the surface of the semiconductor circuit is produced, and the registration features of the topographic record are brought into coincidence with reference features of a reference drawing.

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

Abstract: A process produces at a predetermined metallization level at least one metal track (7) within an intertrack dielectric material (1). The process includes the steps of etching the intertrack dielectric material (1) so as to form a cavity (4) at the position of the track, depositing a conducting barrier layer (5) in the cavity (4), filling the cavity (4) with copper, and depositing a silicon nitride layer (8) on the predetermined metallization level. Between the barrier layer deposition step and the copper filling step, titanium is deposited on at least part of the barrier layer. This titanium will be transformed into TiSi2 (60) during the diffusion of the silicon from the silicon nitride layer (8).

Abstract: An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si1−xGex alloy into which indium is implanted, with 10−5≦x≦4×10−1. A first method for fabricating an indium-implanted transistor is also provided. A multilayer composite film is produced on at least one region of a surface of a silicon substrate where a channel region of the transistor is to be formed. The multilayer composite film includes at least one Si1−xGex alloy layer, in which 10−5≦x≦4×10−1, and an external silicon layer. Indium is implanted into the Si1−xGex alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si1−xGex alloy layer. Additionally, a second method for fabricating an indium-implanted transistor is provided.

Abstract: Several peripheral entities are provided, with each peripheral entity being clocked by its own internal clock signal and being able to access a single-access memory. A priority entity is defined from among the peripheral entities, and the other peripheral entities are defined as auxiliary entities. A repetitive time frame is formulated, regulated by the internal clock signal of the priority entity, and subdivided into several groups of time windows that are allocated to the peripheral entities. One of the peripheral entities is a microprocessor that is disabled for a fixed duration after each memory access request.

Abstract: A method is provided for fabricating a semiconductor device having a gate-all-around architecture. A substrate is produced so as to include an active central region with an active main surface surrounded by an insulating peripheral region with an insulating main surface. The active main surface and the insulating main surface are coextensive and constitute a main surface of the substrate. A fist layer of Ge or an SiGe alloy is formed on the active main surface, and a silicon layer is formed on the first layer and on the insulating main surface. The silicon layer and the first layer are masked and etched in order to form a stack on the active main surface, and the first layer is removed so that the silicon layer of the stack forms a bridge structure over the active main surface. The bridge structure defines a tunnel with a corresponding part of the active main surface.