Abstract: A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level.

Abstract: A MOS technology power device is described which comprises a plurality of elementary active units and a part of said power device which is placed between zones where the elementary active units are formed. The part of the power device comprises at least two heavily doped body regions of a first conductivity type which are formed in a semiconductor layer of a second conductivity type, a first lightly doped semiconductor region of the first conductivity type which is placed laterally between the two body regions. The first semiconductor region is placed under a succession of a thick silicon oxide layer, a polysilicon layer and a metal layer.

Abstract: A method is provided for locally creating an aperture in a metal layer that is formed above a base wafer having at least one lateral mark provided in its peripheral edge and at least one surface mark provided at a point on its surface. Coordinates of a starting position of a tool with respect to the peripheral edge and the lateral mark are found, and coordinates of the position of the surface mark with respect to the starting position of the tool are calculated so as to determine a course to be followed by the tool from the starting position to a working position above the surface mark. The tool is moved to the working position and activated so as to etch the metal layer and create the aperture in the metal layer above the surface mark. Also provided is a device for locally creating an aperture in a metal layer that is formed above a base wafer.

Abstract: A method for communicating between a transmitting unit and a receiving unit. A message formed by elementary messages is transmitted from the transmitting unit to the receiving unit, and at least one reception bit is transmitted from the receiving unit to the transmitting unit. The reception bit (or bits) allows the transmitting unit to determine the elementary message that is to be transmitted next. In a preferred method, at least two reception bits are transmitted from the receiving unit and the values of the reception bits indicate the elementary message that is to be transmitted next by the transmitting unit. The present invention also provides a receiving device for receiving messages from a transmitting device. The receiving device includes an interface for receiving a transmitted message from the transmitting device and for analyzing a received elementary message to determine if it was properly received, and a transmitter for transmitting at least one reception bit to the transmitting device.

Abstract: A device is provided for calculating mutual phase shift of first and second incident signals. The device includes a first pair of blocks associated with the first incident signal, a second pair of blocks associated with the second incident signal, checking circuit, and post-processing circuit. Each of the blocks has storage elements for storing a predetermined set of samples of the corresponding incident signal. In the presence of minimum samples or maximum samples of both incident signals, the checking circuit stores a first set of samples relating to the first incident signal in one of the blocks of the first pair and a first set of samples relating to the second incident signal in the counterpart block of the second pair, and then stores the following sets of samples of each incident signal alternately in the two blocks of each pair. The checking circuit delivers a block validation signal when a set of samples has been completely stored in the storage elements of one of the blocks.

Abstract: A semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each of the inverters is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.

Abstract: A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configuration. The non-modifiable first circuitry selectively imposes one of at least a first potential and a second potential on the configuration node prior to configuration, and the modifiable second circuitry allows modification of the potential imposed on the configuration node by the non-modifiable first circuitry. In a preferred embodiment, the modifiable second circuitry includes at least one fuse that is in an intact state before configuration and that can be changed to a destroyed state after configuration. This enables a reduction in the number of fuses that have to be destroyed during the configuration of the circuit. Also provided is an information processing system that includes at least one configurable electronic circuit having configuration nodes.

Abstract: A method for manufacturing a smart card in which a through-passage is produced in a central sheet. At least one face of the central sheet is provided with at least one metal coil having connection parts, and an electronic chip having electrical connection pads is inserted into the passage. At least some of the electrical connection pads of the chip are soldered to the connection parts of the coil, and the faces of the central sheet are provided with external covering sheets to form a stack of sheets. In a preferred method, the stack of sheets is hot pressed or laminated such that the material of the sheets is flowed and fills the space around the chip. A smart card is also provided. The smart card includes at least one metal coil having at least two connection parts, an electronic chip connected to the connection parts of the coil, a central sheet having a through-passage, and external covering sheets that grip the central sheet. The electronic chip is placed in the passage in the central sheet.

Abstract: A circuit for checking the parity of the contents of a register is provided. The register has a test mode in which a scan input of each flip-flop in the register is connected to a scan output of a preceding flip-flop to form a scan path. The parity checking circuit includes an XOR gate for at least each flip-flop from the second flip-flop to the last flip-flop of the register. Each XOR gate has one input connected to the normal output of the associated flip-flop, another input connected to the scan input for the flip-flop, and an output connected to the scan output of the flip-flop when not in the test mode. The result of the parity checking operation is generated at the output of the XOR gate associated with the last flip-flop of the register. In preferred embodiments, for each flip-flop of the register, the normal output of the flip-flop is supplied to the scan output in the test mode, and the output of the associated XOR gate is supplied to the scan output when not in the test mode.

Abstract: A method is provided for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin. According to the method, a single pin is enabled to receive trimming data by biasing the pin to outside its operating range. A clock signal is obtained from a division of the bias potential of the pin, and the logic value of the trimming data is obtained from a different division of the bias potential of the pin. Serial acquisition of the data is enabled in accordance with the clock signal, and the data is transferred to the modification circuit.

Abstract: A control device is provided for controlling a selector switch of a high voltage input having at least one cascode stage with MOS transistors. The control device includes a reference voltage generation circuit and a control circuit. The reference voltage generation circuit generates reference voltages from the high voltage input and provides one or more output voltages for the biasing of the MOS transistors of the cascode stage. The control circuit controls the reference generation circuit on the basis of a binary control signal, so as to either set the bias voltages at the level of the logic supply voltages to enable the switching of the selector switch even at low values of the high voltage input, or to enable the bias voltages to be set by the reference generation circuit.

Abstract: A digital signal output circuit is provided. The digital signal output circuit includes capacitor forming means connected as an integrator, charging means, discharging means, means for selectively coupling, and a digital signal output. The charging means selectively charges the capacitor forming means with a constant charging current, and the discharging means selectively discharges the capacitor forming means with a constant discharging current. The means for selectively coupling selectively couples the capacitor forming means to the charging means and to the discharging means as a function of data to be transmitted by the digital signal. Additionally, the digital signal output is coupled to the capacitor forming means so as to establish a rising edge of the digital signal when the capacitor forming means is coupled to the charging means and a falling edge of the digital signal when the capacitor forming means is coupled to the discharging means.

Abstract: A test structure includes a single current-measuring means for measuring current between a supply terminal and ground, and first and second branches for measuring capacitance between first and second metal lines. The first branch includes a first switch coupled between the current-measuring means and the first line, and a second switch coupled between the first line and ground. Similarly, the second branch includes a third switch coupled between the current-measuring means and the second line, and a fourth switch coupled between the second line and ground. A method for testing a circuit is also provided.

Abstract: An active pull-up circuit for connection to an input pin that receives high and low logic level signals and a high voltage signal whose level is higher than the high logic level. The active pull-up circuit includes a pull-up circuit that is coupled between the input pin and a voltage supply line, and a breaking circuit that is coupled between the pull-up circuit and the voltage supply line. The pull-up circuit selectively brings the input pin to the level of the voltage supply line, and the breaking circuit operates to inhibit the pull-up circuit when the high voltage signal is on the input pin. In a preferred embodiment, the breaking circuit inhibits the pull-up circuit by electrically isolating the pull-up circuit from the voltage supply line. A method for selectively pulling-up an input node is also provided.

Abstract: A method is provided for communicating on an equipment network. According to the method, a message is sent from a sending equipment unit to a receiving equipment unit as a signal having a nominal power. Whenever the signal is amplified by an intermediate equipment unit through which the signal passes, the message is modified to indicate that the signal has been amplified by the intermediate equipment unit. Also provided is a first equipment unit for connection to an equipment network.

Abstract: An electrical insulation circuit of the type connected between a peripheral circuit and a two-way bus. The electrical insulation circuit includes first and second optocouplers for transmitting differential signals in the peripheral circuit-to-bus direction, and third and fourth optocouplers for transmitting differential signals in the bus-to-peripheral circuit direction. The first and third optocouplers are associated with a first signal terminal on the peripheral circuit side and with a first data wire on the bus side, and the second and fourth optocouplers are associated with a second signal terminal on the peripheral circuit side and with a second data wire on the bus side. Further, the first and third optocouplers and the second and fourth optocouplers are connected such that the first and second optocouplers are off during transmission in the bus-to-peripheral circuit direction and the third and fourth optocouplers are off during transmission in the peripheral circuit-to-bus direction.

Abstract: An electromagnetic transponder is provided that includes an oscillating circuit, an electronic circuit, a rectifying circuit, and a capacitive modulation circuit. The oscillating circuit includes an inductive clement and the electronic circuit includes a transmission circuit for transmitting digitally-coded information. The rectifying circuit is coupled to the oscillating circuit to provide a DC supply voltage to the electronic circuit, and the capacitive modulation circuit is coupled to both end terminals of the inductive element and to the reference potential of the electronic circuit. In a preferred embodiment, the capacitive modulation circuit includes two capacitors, with capacitor being coupled between one end terminal of the inductive clement and the reference potential and the other capacitor being coupled between the other end terminal of the inductive element and the reference potential.

Abstract: Dummy cell test circuit for measuring delay times in embedded, said embedded circuits being connected to access circuits equipped with input access pads and output access pads, between which is comprised an electrical main path, said test circuit comprising a test input pad and a test output pad, between which is comprised an electrical dummy test path. According to the present invention the test input pad correspond to the access input pad (IN1′ IN1″) of the embedded circuit (2).

Abstract: A method for fabricating an integrated circuit. According to the method, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form electrical connection elements, and at least a third dielectric layer is formed. Holes and/or trenches are selectively etched in the third dielectric layer and the second dielectric layer with respect to the first dielectric layer and the elements, in order to control the depth of the etch. Additionally, there is provided an integrated circuit of the type having metallization levels separated by dielectric layers and metallized vias connecting lines of different metallization levels. The integrated circuit includes first and second metallization levels, first and second superposed dielectric layers located above the first metallization level, and a third dielectric layer located above the first and second dielectric layers.

Abstract: A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control signals from data elements received serially through a data transfer input/output device. The method also includes the following steps: (1) extracting a control word included in the data received serially; and (2) decoding the control word extracted in the previous step in order to perform an operation, as a function of the value of the control word, thus modifying the logic state of at least one control signal.