Abstract: A semiconductor device, e.g., a DRAM, having vertical conduction transistors and cylindrical cell gates, which includes a plurality of spaced-apart trench isolation regions formed in a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a silicon pillar formed on each bit line, a gate insulating layer and gate line formed on each silicon pillar in surrounding relationship thereto, a planarizing layer formed in recesses in the gate lines, an insulating layer formed on the upper surfaces of the gate line and planarizing layer, a plurality of contact holes provided in vertically aligned portions of the insulating layer, the gate line, and the gate insulating layer located above respective ones of the silicon pillars, and, a storage node of a capacitor formed with the contact holes and adjacent surface portions of the insulating layer, in contact with the source region of respective ones of the silicon pillars.

Abstract: A row redundancy circuit for use in a semiconductor memory device having one memory cell array, and first and second main row decoders and first and second spare row decoders formed on both sides of the memory cell array includes a first fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the first spare row decoder, a second fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the second spare row decoder, and a row redundancy control circuit for receiving the output signals of the first and second fuse boxes and selectively supplying an output signal responsive to the received input signal level to the first and second spare row decoders.

Abstract: The plasma display panel comprises two substrates onto which parallel cathodes and anodes are attached, respectively. When the anode and cathode substrates are connected together by barriers, which also prevent the cross-talk between pixels, the cathodes and anodes are perpendicular to each other. The cathodes are made of thin metallic wires that attach to the rear substrate. Fabricating the cathode structure comprises the steps of: preparing a compound fiber in which a plurality of metallic lines are arranged in parallel and a plurality of thermoplastic threads are arranged perpendicular to the metallic lines; placing the compound fiber on the rear substrate; and baking this combination.

Abstract: In a television system including a source of an intermediate frequency (IF) signal, which signal includes an IF picture carrier amplitude modulated with video information, synchronous demodulator means responds to the IF signal, for providing an in-phase first output video signal that has both luminance and chrominance components, and for providing a quadrature-phase second output video signal that has a chrominance component but substantially no luminance component. Chroma circuitry is responsive to the quadrature-phase second output video signal for generating first and second color-difference signals.

Abstract: Disclosed is a dynamic random access memory device (DRAM) having an increased cell capacitance and simplified manufacturing method thereof. The storage electrode the capacitor of the DRAM is connected to a semiconductor substrate through an opening formed in an insulating layer, and has a structure having an outer peripheral wall portion with a laterally extending bottom on the insulating layer and an inner central pillar portion including a hole of a certain depth within the opening in the center of the outer peripheral wall portion. Thus, cell capacitance is greatly increased within a limited unit cell area, its reliability is enhanced, and the manufacturing process is distinctly simplified.

Abstract: A circuit parameter adjustment circuit for adjusting a circuit parameter (e.g., resistance or capacitance) of a circuit having N network elements connected between two nodes. The circuit parameter adjustment circuit includes N zapping devices and N switching devices coupled between the N zapping devices and the N network elements. When a zapping control signal is low, the N switching devices are directly responsive to respective ones of the N trimming signals for bypassing or not bypassing the respective ones of the N network elements, thereby facilitating testing of the value of the circuit parameter for different combinations of the trimming signals, prior to zapping the zapping devices. Then, after the optimum combination of trimming signals has been selected, the zapping control signal is driven high, whereby the N zapping devices are zapped or unzapped, depending upon the logic level of the respective ones of the N trimming signals.

Abstract: An arrangement for vertically mounting a semiconductor device to a substrate, e.g., a printed circuit board (PCB), in which a plurality of sequentially arranged external leads of the semiconductor device include at least three different sets of non-consecutive ones of the external leads which have laterally outwardly extending foot portions lying in respective, vertically spaced-apart planes, and in which the foot portions of first and second ones of the sets of non-consecutive external leads are respectively secured to respective first and second steps formed in one of a plurality of walls defining a cavity in the PCB, and a third set of the non-consecutive external leads are secured to a portion of a major surface of the PCB adjacent the cavity.

Abstract: An error correction system including a syndrome modifier for receiving a syndrome and operating the equation ##EQU1## where i is an integer greater than or equal to zero, for transforming the syndrome into a new syndrome; an n-1 error correction circuit for receiving the syndromes modified by the syndrome modifier for n-1 error correction, a counter for varying the K value if the n-1 error correction fails; a circuit for outputting an .alpha..sup.K value corresponding to the K output signal of the counter, to the syndrome modifier, an error value operation circuit for receiving the output signal of the n-1 error correction circuit to calculate a substantial error value according to the equatione.sub.i =e'.sub.i /(1+.alpha..sup.i-k)where i is an integer greater than or equal to zero; and an adder for receiving and adding the output signal and the syndrome from the error value operation circuit, to perform a final error correction.

Abstract: A method for correcting multiple erroneous symbols included in data produces a demodulation flag indicating whether demodulation based on a modulation code such as EFM or ETM is possible. The demodulation flag is used in decoding the data based on the error correcting code. Producing the error locations during decoding in accordance with a Reed-Solomon code comprises the steps of producing an index using ##EQU1## provided .sigma..sub.1, .sigma..sub.2 and .sigma..sub.3 represent coefficients of an error location polynomial, k.sub.1 represents .sigma..sub.1.sup.2 +.sigma..sub.2 and k.sub.2 represents .sigma..sub.1 .sigma..sub.2 +.sigma..sub.3, reading out virtual roots from a specified memory related to the index, and transforming the virtual roots (Z.sub.1, Z.sub.2 and Z.sub.3) into error locations (x.sup.j1, x.sup.j2 and x.sup.j3) in accordance with the following equations.x.sup.j1 =Z.sub.1 (k.sub.1)+.sigma..sub.1x.sup.j2 =Z.sub.2 (k.sub.1)+.sigma..sub.1x.sup.j3 =Z.sub.3 (k.sub.1)+.sigma..sub.

Abstract: An internal supply voltage generation circuit, producing an internal supply voltage during a normal mode of operation and an external supply voltage during a burn-in mode of operation. The circuit including a plurality of fuses, the operation of which establishes the burn-in mode of operation, and controls a variable burn-in voltage level.

Abstract: An electrically erasable programmable read only memory (EEPROM), having error checking and correction circuitry uses a separation circuit to electrically isolate a temporary page buffer memory from a memory array so that better reliability of parity generation and error correction is provided. The EEPROM memory array includes a plurality of bit lines, a plurality of memory cells respectively connected to the bit lines and parity cells. The error check and correction circuit includes a column gate logic, connected to the plurality of bit lines, for temporarily loading randomly input data onto a memory page buffer. The EEPROM processes the data in the page buffer to logically store it as multi-byte data, simultaneously together with appropriate parity bit data corresponding to each multi-byte data set, in the memory array.

Abstract: A storage electrode of a capacitor of a semiconductor memory device and a method for manufacturing the same are disclosed. A first electrode of the capacitor comprises a main electrode having a plurality of microtrenches and micropillars formed therein, an outer wall surrounding the microtrenches and micropillars, a granular silicon layer formed on an outer sidewall of the outer wall, and a column electrode supporting the main electrode and electrically connecting the main electrode to a source region of a transistor of the semiconductor device. The first electrode preferably has a horizontally fin-structured auxiliary electrode formed underneath the main electrode and electrically connected to the column electrode of the first electrode. The capacitor may be formed by using an etching end-point detection layer and an HSG polysilicon layer. The effective surface area of the storage electrode of a capacitor is increased to thereby obtain adequate cell capacitance.

Abstract: In a method for forming an isolation region in a semiconductor device, after forming a first oxide film and a silicon film on a semiconductor substrate, an oxidation-blocking film is formed on the silicon film. Then, a high-temperature heat treatment process is performed in a nitrogenous atmosphere. The oxidation-blocking film is selectively etched to form an opening, and a thermal oxidation process is performed to form a thermal oxide film in the opening. A bird's beak between the oxidation-blocking film and the silicon film is suppressed because of the heat treatment in a nitrogenous atmosphere, so that stable isolation characteristics can be secured.

Abstract: Disclosed herein is an all-optical regenerator including two stripe waveguides, each waveguide having an input and an output optical contacts; a nonlinear ring resonator comprising a source laser, a multi-sectional semiconductor laser, mirrors, four phase modulators, and means for controlling the source laser, the multi-sectional laser and the four phase modulators; and two directional couplers, each coupler being positioned between the nonlinear ring resonator and each of the waveguides. The all-optical regenerator in accordance with the present invention performs such functions as clock recovery, pulse reshaping and amplification of optical signals without going through intermediate electronic stages.

Abstract: A high-performance television receiver synchronously detects the picture IF signal. A synchronous impulse noise in the IF signal generates either positive-going noise or negative-going noise in the video signal supplied from a synchronous video detector, which noise is subsequently replaced by a value of video signal occurring previous to the impulse noise in the following manner. The video signal contaminated with impulse noise is supplied as input signal both to an impulse noise detector and to a delay line. The output signal from the delay line, delayed by about 240 ns, is supplied as the signal for tracking by a track-and-hold circuit. The detected impulse noise signal is used to actuate the hold condition in the track-and-hold circuit. By stretching the pulse from the impulse noise detector for the 600-800 ns duration overlapping the duration of most impulse noise, the track-and-hold circuit replaces most impulse noise with previously stored values of the delayed video signal.

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract: A projection method uses a modified illumination method for a lithography process of semiconductor device, and a projection system and mask use the projection method. An object is exposed by removing the vertical incident component of light passed through a condenser lens. Zero-order diffracted light interferes destructively and the oblique component of .-+. first-order diffracted light, interferes constructively. The obliquely incident component light illuminates a mask having a pattern formed thereon. The vertical incident component of the light is removed by a phase difference of light due to a grating mask or a grating pattern formed on the back surface of the conventional mask. The resolution of a lithography process is improved due to the increased contrast, and the depth of focus is also increased. Thus, patterns for 64 Mb DRAMs can be formed using a conventional projection exposure system.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device. A conductive layer is formed on the semiconductor substrate and a photoresist pattern is formed on the conductive layer. The conductive layer is etched, using the photoresist pattern as a mask to form a first step-portion in the conductive layer. A first spacer is formed on a sidewall of the photoresist pattern, which may be formed by flowing the photoresist pattern. The conductive layer is etched, using the first spacer as a mask, to form a second step-portion in the conductive layer. The photoresist pattern and the first spacer is removed. A first material layer is formed on the entire surface of the resultant structure and etched to form a second spacer on the sidewalls of the first and second step-portions. The conductive layer is etched, using the second spacer as a mask, to form a storage electrode of a capacitor. Cell capacitance may be increased by a simple process, and the heat cycle may be reduced.

Abstract: A method for forming contact holes having different depths in an insulating layer which covers a semiconductor substrate. A first step selectively etches the upper parts of the insulating layer which correspond to contact holes having a greater depth than the shallowest contact hole, using a first mask pattern. A second etch step selectively etches the remainder of the insulating layer for all of the contact holes at the same time using a second mask pattern. Thus, contact hole misalignment is kept to a minimum.

Abstract: The present invention forms a intermediate layer between a conductive layer and BPSG layer. In one embodiment, this intermediate layer is a buffer layer that absorbs excess P ions from the BPSG layer to suppress the formation of bubbles and thereby prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer. In the second embodiment the intermediate layer is a thin nitride layer, which prevents the conductive layer and BPSG layer from being in direct contact with each other to suppress the formation of bubbles and also prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer.