Abstract: An apparatus and method is provided for forming shaped food products from an emulsion or batter. A stuffing tube includes a wall defining a central passage for emulsion, and a treating fluid passage positioned within the wall and radially outside of the central passage. The stuffing tube is slideably mounted coaxially within a mold tube. Emulsion and treating fluid are deposited into the mold tube during retraction of the stuffing tube from the mold tube, where the depositions occur substantially without relative motion between the emulsion and the treating fluid, or between the emulsion/treating fluid and the inside of the mold tube. A production machine incorporating an array of stuffing tubes can be indexed with a plurality of arrays of mold tubes.

Abstract: A semiconductor package with a chip supporting member is provided, including a lead frame having a die pad and a plurality of leads, and a chip supporting member mounted on a central portion of the die pad. The chip supporting member has a first surface and an opposing second surface attached to the die pad. At least a chip is mounted on the first surface of the chip supporting member to space the chip apart from the die pad via the chip supporting member, so as to prevent the chip from being damaged by thermal stress induced by CTE (coefficient of thermal expansion) mismatch between the chip and lead frame, thereby eliminating delamination, warpage and chip cracks. Moreover, the chip supporting member interposed between the chip and die pad provides greater flexibility for mounting variously sized or shaped chips on the die pad without having to use chips corresponding to profile of the die pad.

Abstract: The invention relates to a process for automatically determining the image quality of inkjet photo printers or color inkjet photo printers, whereby a digital reference test chart is produced which is made available to the printer. The printer or photo printer prints out the reference test chart so that a photo printer specific printout of the reference test chart is generated, which is digitized for comparison of the digitized image data with an optimum digital reference test chart, for determination of the image quality of the printed image on the basis of deviations or concurrences between the photo printer specific test chart printout and the reference test chart.

Abstract: An apparatus and method is disclosed for forming an emulsion or batter into shaped food products without the use of a casing. The apparatus includes a hollow stuffing tube connected to a source of suitable proteinaceous emulsion, and a molding tube mounted about the stuffing tube, the molding tube having an open end and a closed end. A supply of emulsion is conveyed under pressure into the stuffing tube to form a continuous length of shaped emulsion. Then, the shaped emulsion is directed into the molding tube, where the pressure of the emulsion bears against the closed end of the molding tube and causes the molding tube to move relative the stuffing tube. A treating fluid is directed to the interior surface of the molding tube, such that the interior surface is continuously wetted and evenly coated by the treating fluid, thereby forming a proteinaceous skin about the shaped emulsion.

Abstract: Pseudo-impulse display for reducing after-images during display of moving images in an active matrix type display apparatus. Liquid crystal capacitors are formed at intersections of signal lines and scanning lines to display images. Auxiliary capacitors are provided for keeping a potential difference across the liquid crystal capacitors during display. One of the two electrodes of the auxiliary capacitors is connected to a switching element together with a pixel electrode. After the liquid crystal capacitor and the auxiliary capacitor have been charged with a video signal on the signal lines while the switching element is selectively put into the conducting state with the scanning lines, and after a predetermined time has passed, an auxiliary capacitor driver applies a signal to the other electrode of the auxiliary capacitor, such that the display luminance due to the liquid crystal capacitor is reduced.

Abstract: A process for forming an in-plane switching mode liquid crystal display (IPS-LCD), which defines pixel portions of the common and data electrodes by the same photo-masking and lithography procedure, is disclosed. Accordingly, the misalignment can be avoid. An in-plane switching mode liquid crystal display (IPS-LCD) is also disclosed. The IPS-LCD includes a storage capacitor consisting of storage-capacitor portions of the common and data electrode structures, which is disposed outside the pixel region so as to enhance the aperture ratio of the pixel region.

Abstract: An MEOMS sensing chip for optically detecting and measuring substances in fluid samples is disclosed. The MEOMS sensing chip includes a system for optically sensing substances in the fluid samples and a system for delivering the fluid samples to the sensing system. The sensing system includes a two-branch channel waveguide and a plurality of ring waveguides, each branch in the two-branch waveguide being used for evanescently coupling light energy into one of the ring waveguides. The delivering system includes a plurality of micro-channels and a plurality of micro-wells, the micro-channels being used for transporting the fluid samples to the micro-wells. Each micro-well is aligned with a respective ring waveguide and is used for exposing the fluid sample contained therein to the respective ring waveguide. Characteristics related to the evanescent coupling of the light energy into the ring waveguides, e.g., resonant frequencies of the ring waveguides, are used for detecting substances in the fluid samples.

Abstract: A semiconductor package with a heat dissipating structure is provided. The heat dissipating structure includes a flat portion, and a plurality of support portions formed at edge corners of the flat portion for supporting the flat portion above a chip mounted on a substrate. The support portions are mounted at predetermined area on the substrate without interfering with arrangement of the chip and bonding wires that electrically connect the chip to the substrate. The support portions are arranged to form a space embraced by adjacent supports and the flat portion, so as to allow the bonding wires to pass through the space to reach area on the substrate outside coverage of the heat dissipating structure; besides, passive components or other electronic components can be mounted on the substrate at area within or outside the coverage of the heat dissipating structure, thereby improving flexibility in component arrangement in the semiconductor package.

Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on the substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced heat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.

Abstract: An improved tape carrier package (TCP) structure is proposed, which is characterized in the provision of dummy pads and dummy leads to help reinforce the package construction. The dummy pads are provided on the corners of the semiconductor chip, while the dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas on the tape carrier. During assembly, since dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas, the corners of the semiconductor chip can be firmly supported as well as the four sides of the semiconductor chip which are supported by the I/O leads. As a result the package construction is reinforced. During inner-lead bonding (ILB) process, such reinforcement can help prevent the cracking of the I/O leads.

Abstract: A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.

Abstract: The invention relates to an arrangement for preparing a liquid treatment solution for treating photosensitive material, said arrangement including a storage container for storing fresh treating solution to be fed to a development compartment of a development apparatus, a supply portion for supplying a dry component or components and/or one or several mixtures of components for preparing the treatment solution and a reception container for receiving a solvent, wherein according to the invention a mixing tank is interposed between said supply portion, said reception container and said storage container.

Abstract: A semiconductor package with a crack-preventing member is proposed, in which a chip is mounted on a chip carrier by means of an adhesive and is electrically connected to the chip carrier. The crack-preventing member is formed at a proper position on the chip, and generates compression stress on the chip to sufficiently counteract tension stress produced from the chip carrier and adhesive in a molding process. This can effectively prevent the chip from cracking during molding, and thus improve the quality of fabricated products.

Abstract: A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip. The proposed semiconductor packaging technology is based on a specially-designed leadframe which is formed with a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus for the packaged chip, and the ground wing is electrically linked to the chip-support-and-grounding structure. After encapsulation process is completed, the ground wing as well as the outer lead portions are exposed to the bottom outside of the encapsulation body, which can be then bonded a PCB's ground plane during SMT (Surface Mount Technology) process, thus enhancing the grounding effect and the electrical performance of the packaged chip during operation.

Abstract: A window-type multi-chip semiconductor package is provided. A first chip and a second chip are mounted on a surface of a substrate formed with an opening, and a third chip is stacked on the first and second chips, wherein a plurality of bonding wires formed through the opening are used to electrically interconnect the chips and electrically connect the chips to the substrate. The chips are encapsulated by a first encapsulant formed on the surface of the substrate, and a second encapsulant is formed on an opposing surface of the substrate for encapsulating the bonding wires. With the chips being mounted on the same surface of the substrate, conductive elements such as bond pads formed on the chips are arranged toward the same direction and facilitate shortening of the bonding wires, thereby enhancing electrical transmission and performances for the semiconductor package.

Abstract: A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

Abstract: An information exchanging device is disclosed. The information exchanging device includes two separate but engagable housings which are mounted thereon two connectors for electrically connecting to two handy personal information processing devices such as PDAs or cellular phones, respectively. The two connectors are electrically connected to each other via an information exchanging circuit after the two housings engages with each other. The information exchanging circuit can be further connected to a personal computer. The information exchanging operation between the two handy personal information processing devices is performed in response to a triggering signal generated by pressing an actuating button or manipulating the personal computer.

Abstract: An image formation apparatus to ensure provision of sheets used in a host mode process and a guest mode process without increasing the number of sheet cassettes to be mounted at a sheet feed unit and to prevent tedious task due to increase in the sheet feed frequency is provided. In the image formation apparatus, the main CPU identifies the accommodated number of sheets n in the sheet cassette every time one copy mode image formation process ends. This value n is compared with a set value of the number of sheets N read out via a sub CPU. When value n is equal to or less than value N, the copy mode image formation process is interrupted until the sheet cassette is replenished with sheets while waiting for input of image data associated with the guest mode image formation process. When image data associated with the guest mode image formation process is input from an external device during this period, the guest mode image formation process is executed.

Abstract: A substrate for accommodating a passive component is proposed, including a core layer defined with a chip attach area and a trace forming area surrounding the chip attach area, with a solder mask layer being applied on the trace forming area. At least a pair of solder pads are formed on the trace forming area, and partly exposed to outside of the solder mask layer. The solder pads are each formed at a central position with an recess, allowing the core layer to be partly exposed through the recesses of the solder pads. For bonding a passive component to the solder pads, solder paste soldered on the solder pads forms a recessed top surface due to surface tension of the solder paste, and generates a downward and convergent dragging force for properly positioning the passive component on the solder pads without producing shifting or tombstone effect.

Abstract: A fabricating method for a semiconductor package is proposed, in which a chip carrier accommodates at least one semiconductor chip, which is attached with an interface layer formed on a covering module plate consisting of at least one covering plate, while the interface layer is poor in adhesion to the chip and a molding compound used for forming an encapsulant. So that after completing molding, ball implantation and singulation processes, the interface layer, the covering plate and a portion of the encapsulant formed on the covering plate can be easily removed by heating the singulated semiconductor package. This allows the molding compound not to flash on the chip, and prevents the chip from being damaged by stress generated in the molding process.