Abstract: A temperature regulation and flow control device is described. A web of material, e.g., for a wet suit, has a layer of gel particles embedded in a flow control layer, preferably a foam matrix. A water permeable neoprene layer covers the flow control layer and allows water to enter the suit. The flow of water in the suit is regulated by the expansion and contraction of the gel as it undergoes a volume phase transition in response to a change in temperature. When the diver is in cold water, the cold water enters the foam substrate and the gel expands, causing permeability (i.e., flow) to decrease. Flow is restricted in response to cooling, and the foam substrate expands and tightens the fit of the wet suit. In warmer water, an opposite effect occurs, whereby the gel contracts and flow increases. The gel contracts relaxing the fit of the suit. A gel having a particular volume phase transition critical temperature is selected in order to maintain body temperature in a particular environment.

Abstract: A semiconductor package with a heat dissipating structure is provided, including a lead frame with a die pad for allowing a chip to be mounted on an upper surface of the die pad, and a heat sink abutting against a lower surface of the die pad. A top surface of the heat sink, in contact with the lower surface of the die pad, is formed with at least a recessed portion. During a molding process of using a resin material to form an encapsulant for encapsulating the chip, lead frame and heat sink, the resin material fills into the recessed portion and forms a supporting member between the die pad and heat sink to provide support for a central portion of the die pad, so as to prevent the chip from cracking in a step of building up a packing pressure of the molding process, thereby assuring yield and reliability of fabricated products.

Abstract: An encapsulated semiconductor device includes a lead frame formed with a flash-proof body. The flash-proof body includes a dam bar formed on atop surface of the lead frame and a tape adhered to a bottom surface of the lead frame, where the dam bar is attached to both the lead frame and the tape. The semiconductor device further includes an encapsulation body having a core-hollowed portion integrated with the lead frame, the core-hollowed portion being bordered by the dam bar and the tape so that a semiconductor chip and conductive elements are exposed in the encapsulation body. A lid can be adhered to the encapsulation body to air-tightly seal the semiconductor chip and encapsulation elements in the core-hollowed portion.

Abstract: A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: A multi-mode input control device for use with a computer via a graphic user interface (GUI) is disclosed. The input control device may optionally perform functions of a mouse device and a trackball device. The mouse and trackball devices share the same key switch, control unit, interface circuit, and signal channel to the computer, which are included in the mouse device. In the mouse mode, the mouse device is individually moved to perform the input control operation in a conventional manner. For the trackball mode, a first signal connector of the trackball device and a second signal connector of the mouse device are connected to each other so that the trackball device can perform the input control operation via the mouse device.

Abstract: The invention relates to a device and a method, as well as a computer program product, for measuring a physical or physiological activity by a subject and for assessing the psychosomatic state of the subject. The subject is automatically provided with a sequence of different sensory stimuli by means of a stimulus generator controlled by a control means. Electrical signals are then derived from a physical or physiological activity by the subject in response to each sensory stimulus provided, in particular a force of pressure exerted on a letter balance. The electrical signals are compared with a pre-settable index value. On the basis of this, information can be obtained about the psychosomatic state of the subject, in particular about preferences and inclinations. The device is preferably used as an allergy testing apparatus, wherein the sensory stimuli provided in the sequence represent substances which potentially trigger allergies.

Abstract: A semiconductor device and a fabrication method of the same are proposed, in which at least one electronic component is firstly mounted on a first substrate, and then the first substrate is attached onto a semiconductor chip or a second substrate. Further, with the chip being deposited on the second substrate, electrical connection is established among the first substrate, the second substrate and the chip. This combined structure is subsequently subjected to molding, ball implantation and singulation processes, and thus completes the fabrication of the semiconductor device. Such a semiconductor device provides significant advantages, including prevention of the occurrence of wire short-circuiting, no need to alter the substrate design, no need to use a circuit pattern with fine pitches or an expensive substrate integrated with electronic components.

Abstract: To reduce the total bit-line capacitance in a semiconductor memory arrangement, it is proposed that the semiconductor memory arrangement be so divided into a plurality of memory blocks (9) that each memory block (9) has a corresponding data bus and a group of sense amplifiers (1) connected to this data bus (2) associated with it. In this way it is possible for the bus-line capacitance (CB), which contributes to the total bit-line capacitance, to be reduced because the bus-line capacitance then depends simply on the length of a memory sector (6).

Abstract: A low profile stack semiconductor package is proposed. A lower chip having centrally-situated bond pads is mounted on a substrate, and electrically connected to the substrate by bonding wires. A cushion member is peripherally situated on the lower chip, allowing the bonding wires to extend from the bond pads in a direction parallel to the lower chip, and to reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate. An adhesive is applied on the lower chip, for encapsulating the bond pads, cushion member and bonding wires. This allows an upper chip to be readily stacked on the lower chip by attaching the upper chip to the adhesive, without affecting or damaging structural or electrical arrangement formed on the lower chip.

Abstract: A multi-chip semiconductor package is proposed, in which a lead frame is formed with a chip carrier that consists of at least one supporting frame and a plurality of downwardly extending portions integrally formed with the supporting frame. As the chip carrier occupies small space, this does not impede flowing of a molding compound used for forming an encapsulant. The adjacent extending portions are provided with sufficient space therebetween for allowing the molding compound to flow through the space, so that problems of incomplete filling with the molding compound and the formation of voids can be eliminated. Moreover, the downwardly extending portions can function as a pre-stressed structure so as to closely abut a bottom of a mold cavity after mold engagement, thereby making the chip carrier well assured in position without being dislocated.

Abstract: A dual-die integrated circuit package is provided, which can be used to pack two semiconductor dies in the same package unit. These two semiconductor dies are of the type having an array of bonding pads formed thereon. The dual-die integrated circuit package has a first leadframe and a second leadframe, each having a die pad and a plurality of leads, with the die pad being arranged at a different elevation with respect to the leads. The two semiconductor dies are mounted on the respective die pads of the two leadframes, with the bottom surface of each semiconductor die facing the bottom surface of the other, allowing the bottom surface of one semiconductor die to be separated from the die pad of the first leadframe and the bottom surface of the other semiconductor die to be separated from the die pad of the second leadframe.

Abstract: A method is proposed for mounting a passive component, such as a resistor or a capacitor, over an IC package substrate, such as a BGA (Ball Grid Array) substrate. Conventionally, the mounting of a passive component over a substrate would result in the undesired existence of a gap between the passive component and the substrate, which could lead to such problems as bridged short-circuit, popcorn effect, and dismounting of the passive component during subsequent processes. As a solution to these problems, the proposed method utilizes an electrically-insulative material, such as epoxy resin, to fill up the gap between the passive component and the substrate. Various techniques can be employed to fill the electrically-insulative material into the gap, including dispensing and stencil printing.

Abstract: A ball grid array semiconductor package is proposed, wherein at least a chip is mounted on a substrate, and signal pads on the chip are electrically connected to signal fingers on the substrate by bonding wires. A power plate and a ground plate are each attached at two ends thereof respectively to predetermined positions on the chip and substrate, without interfering with the bonding wires. No power ring or ground ring is necessarily formed on the substrate, thereby reducing restriction on trace routability of the substrate. Further, with no provision of power wires or ground wires, short circuit of the bonding wires is less likely to occur, and thus production yield is enhanced. In addition, the power plate and ground plate provide shielding effect for protecting the chip against external electric-magnetic interference, and are partly in direct contact with the atmosphere for improving heat dissipating efficiency of the semiconductor package.

Abstract: In order to achieve a maximally space-saving configuration of a matricial memory arrangement (1), for example in the form of a non-volatile flash memory, which comprises a plurality of memory cells (3) grouped into memory sectors (2), it is proposed to use regular memory cells (4) of this memory arrangement (1) as sector switches for selecting/activating the respective memory sector (2). In order to avoid the effect of high voltages on the threshold voltage of the memory cells (4) configured as sector switches, the “floating gate” (FG) of these memory cells (4) may be short-circuited to the “control gate” (CG).

Abstract: A lead-on-chip type of semiconductor package with an embedded heat sink is constructed on a leadframe including an outer-lead portion, an inner-lead portion, and a downset bond-finger portion. A semiconductor chip is arranged on a back side of the inner-lead portion, with its active surface being attached to the downset bond-finger portion. Then, a plurality of bonding wires are bonded between I/O pads of the chip and the downset bond-finger portion. Further, a heat sink is adhered to a front side of the inner-lead portion by an electrically-insulative and thermally-conductive adhesive material. Finally, an encapsulation body is formed to encapsulate the chip, the inner-lead portion of the leadframe, the bonding wires, and the heat sink. Owing to the embedded heat sink configuration, it allows the packaged chip to have good heat-dissipation efficiency during operation and also allows the overall package body to be made very compact in size.

Abstract: A lead frame and a flip chip semiconductor package having the lead frame are proposed, in which a die pad of the lead frame is elevated with a height difference relative to leads of the lead frame, and the height difference cannot exceed the vertical height of a plurality of solder bumps, which electrically connect a semiconductor chip to the lead frame. In a reflow process, due to good wetability of the lead frame, the solder bumps keep collapsing, allowing the semiconductor chip placed above the die pad to gradually move downwardly until abutting the die pad, which then stops the chip from moving, so as to force the solder bumps to stop collapsing to be maintained with a certain height. This therefore helps eliminate the occurrence of over-collapsing of the solder bumps, and thus assure bonding quality between the solder bumps and the lead frame.

Abstract: Disclosed is a semiconductor package which has no resinous flash formed on a lead frame and its manufacturing method.

Abstract: A semiconductor package is proposed, in which at least one chip is mounted on a substrate, and at least one die-attach region is formed on the substrate. A plurality of thermal vias formed in the die-attach region and penetrating the substrate, in a manner that the thermal vias each has a top end connected to the chip mounted on the substrate and a bottom end connected to a thermal pad formed beneath the substrate at a position corresponding to the die-attach region. The thermal pad has a surface directly exposed to the atmosphere, allowing heat generated by the chip to be dissipated through the thermal vias and the exposed surface of the thermal pad to the atmosphere, so as to significantly improve heat dissipating efficiency for the semiconductor package.

Abstract: A tray for ball grid array (BGA) semiconductor packages is provided, composed of a body, protruding portions and positioning portions. The body is formed with a plurality of recessed cavities, and the protruding portions are formed in the recessed cavities corresponding to area free of solder balls on the semiconductor packages to come into contact with the semiconductor packages; this does not require the use of flanges formed in a conventional tray to support a quite narrow peripheral portion of a semiconductor package, thereby preventing cracks of solder balls and assuring structural integrity and electrical-connection quality of the semiconductor packages. When the trays are vertically stacked, a positioning portion of an upper tray is engaged with a gap between an inner side wall of a recessed cavity and a semiconductor package received in a lower tray, so as to securely position the semiconductor packages accommodated by the lower tray.