Abstract: The present invention is directed to a method and apparatus for reducing the frame buffer size in a 3D graphics system. According to an exemplary aspect of the present invention, sorting and limiting the polygons that get processed at a given time may reduce the size of the frame buffer requiered in a graphics system. This may allow the system to process only those polygons that fall in one section of the screen. As a result, the system may not need to double buffer the whole screen. In a preferred embodiment, the location of the screen that gets processed may be arbitrary but should be preferably chosen so it is easy to sort the polygons and time-manage the process as the system needs to know when to swap from one location to another.

Abstract: A rivet setting device for setting a self-tapping rivet in a work piece includes a rotatable head for rotating a self-tapping rivet to form a hole in the work piece and a shank retracting assembly for compressing and spreading the hollow body of the self-tapping rivet, allowing the head of the self-tapping rivet to detach from the shank upon application of a predetermined tensile force. The rotatable head comprises a clutch having a body enclosing a plurality of bearings circumferentially located around the shank, for gripping the shank. The clutch is formed with a plurality of tapered channels for urging the bearings into engagement with the shank upon rotation of the clutch.

Abstract: In a computer system, a bus adapter processes bus operation information structures for performing bus operations by automatically starting processing each bus operation information structure after completing processing the previous bus operation information structure. A processor forms the bus operation information structures and sets control over each bus operation information structure to a sequencer for processing. When a next bus operation information structure is ready for processing after completing processing the previous bus operation information structure, the sequencer checks whether it has control over the next bus operation information structure, and if so, begins processing the next bus operation information structure without being instructed to do so by the processor.

Abstract: A method and system for selectively interconnecting two SCSI host buses where each SCSI host bus includes a host device and multiple addressable SCSI target devices, each SCSI target device having a multibit SCSI ID associated therewith. A SCSI cross-link repeater is interposed between the two SCSI host buses and selectively enabled. Each time the SCSI cross-link repeater is enabled, the repeater enable signal is utilized to automatically alter the most significant bit of the multibit SCSI ID associated with each SCSI target device on the second SCSI host bus, such that those SCSI target devices do not duplicate the SCSI IDs of the SCSI target devices on the first SCSI host bus. Disabling the SCSI cross-link repeater automatically resets the most significant bit of the multibit SCSI IDs, restoring the original SCSI IDs for those devices.

Abstract: The present invention is a method for controlling a ground vehicle, for automated steering control of the vehicle or the like. The method of the present invention includes using a GPS receiver or the like and an inertial gyro or the like for providing automated steering control of the ground vehicle. A difference between a measured off-track error and a lateral error command is fed into a lateral error control loop, producing a lateral velocity command. Then, a difference between a measured lateral velocity and the lateral velocity command is fed into a lateral velocity control loop, producing a yaw rate command. Finally, a difference between a measured yaw rate, the yaw rate command, and a curved track yaw rate for the intended path of the vehicle is computed and fed into a yaw rate control loop, producing a valve command for steering the ground vehicle on or towards its intended path.

Abstract: A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.

Abstract: A plate joiner including a fence support, a drive, and a fence system. The fence support includes a cutter and a contact surface, which defines a cutter slot. The cutter is arranged and configured to protrude from fence support through cutter slot to make a plunge cut into a surface of a workpiece when the contact surface is pressed against the surface and the cutter is plunged into the workpiece by pushing on a rearward handle portion of the tool. The drive is arranged and configured to rotatably drive the cutter through a motor. A preferred fence system includes an angle adjustment system arranged and configured to position the fence at a wide range of fence angles and, at any selected distance from a top face of the workpiece to the fence, the distance from the top face of the workpiece to the cutter remains constant as the front fence angle is adjusted. A preferred fence system includes a trunnion which pivotally couples the front fence to the fence system.

Abstract: A method of increasing computer system bandwidth for computer system having two or more memory complexes is disclosed in which exclusive OR operations are performed on the data from the data regions to generate parity information which is stored in the same single cache pool as the data regions. By using a single cache pool for related data regions, bandwidth and performance are improved.

Abstract: A deformable wedge clamp assembly includes a body having first and second apertures formed therein, the first aperture being suitable for receiving a fastener and the second aperture being suitable for receiving a member to which the body is to be attached and a wedge assembly disposed in the body adjacent to the first and second apertures, wherein insertion of a fastener into the first aperture is capable of deforming the body for moving the wedge assembly against a member received in the first aperture to clamp the body to the member.

Abstract: An apparatus and method for sharing a boot volume among server blades. The shared boot volume may be a single drive or a RAID volume. The shared boot volume is first partitioned into boot slices. Next, individual boot slices of the shared boot volume are correlated with individual server blades, which share the shared boot volume. When a boot slice is correlated with a server blade, the boot slice is presented to the server blade, and the server blade sees the boot slice and only the boot slice, and owns the boot slice. This correlation is transparent to the OS or applications on a given server blade, because the I/O controller masks all boot slices but the one owned by that server blade. As far as OS and applications are concerned, the server blade just has a single boot slice as a dedicated local drive.

Abstract: A sleeve assembly is provided for a package. The package provides storage for a variety of items. A sleeve at least partially surrounds the package and connects to the package through a connection point. The sleeve includes a reinforced adhesive material which provides reinforcement to the connection point and prevents both tearing of the sleeve and displacement of the sleeve from the package.

Abstract: An apparatus which enables a user of a pneumatic tool device, such as a nail gun, to determine the required compressor pressure needed to most effectively utilize the pneumatic tool device and maximize the life of the tool. A compressor pressure indication assembly on a nail gun comprising a nail verification assembly and a readout assembly enables a user to verify the length and/or diameter of the nails to be driven by the nail gun and set the compressor pressure accordingly.

Abstract: The present invention discloses a system and method for optimizing remote data distribution. A system and method for optimizing remote data includes receiving a request for content at a first storage device. The first storage device may include a map which may be analyzed to determine if a copy associated with the content request is present at the first storage device. The map may include at least one map entry having an identifier suitable for describing a range of addressable data blocks. If a copy associated with the content request is initially present, the copy may be provided to a user that requested the content. If the requested content is not initially present, a copy of the content may be retrieved by the first storage device from a second storage device. After receipt of the copy, a map located at the first storage device may be updated to reflect storage of the copy of requested content at the first storage device.

Abstract: The present invention is directed to a system and method for increased data availability. In an aspect of the present invention, a method includes receiving a SMART indication from a data storage device included in a plurality of data storage devices configured as a RAID array. Data from the data storage device which originated the SMART indication is replicated to a second data storage device. The second data storage device was not originally configured in the RAID array with the plurality of data storage devices for data storage. The data storage device which originated the SMART indication from the RAID array is removed, thereby resulting the second data storage device and the plurality of data storage devices configured as a RAID array.

Abstract: A switched architecture for dual, independent storage controllers overcomes latency and coherency problems by an inter-controller command interchange scheme. The switched architecture permits a read or write command to be presented to either storage controller to effect data transfer on the same or the other storage controller. Communication between the two storage controllers is effected through internal Infiniband switches.

Abstract: The present invention is directed to a system and method for coevolutionary circuit design. A system suitable for providing integrated circuit design may include a memory suitable for storing a first set of instructions and a second set of instructions and a processor communicatively coupled to the memory. The processor is suitable for performing the first set of instructions and the second set of instructions. The first set of instructions is suitable for configuring a processor to provide an integrated circuit development environment in which a support methodology for an integrated circuit is created. The second set of instructions is suitable for configuring a processor to provide tools for implementing a platform architecture of an integrated circuit in which the platform architecture supplies a structure of the integrated circuit.

Abstract: The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.