Abstract: One aspect of the invention relates to a composite member for a resonator having an active piezoelectric element and a passive piezoelectric element. The active piezoelectric element causes the resonator to vibrate and detects the frequency of the vibration. The passive piezoelectric element changes the frequency of the vibration. Another aspect of the invention relates to a method for controlling a resonator with composite member having a substrate carrying a composite piezoelectric element. The composite piezoelectric element includes an actuator element, a sensor element and a passive element. The method comprises inducing a resonance within the composite member with the actuator element, detecting the resonance with the sensor element, and altering the resonance by altering the electromechanical coupling of the passive element. Additional aspects and benefits of the invention are also given.

Abstract: The present invention is directed to a structure comprised of alternating layers of metal and sacrificial material built up using standard CMOS processing techniques, a process for building such a structure, a process for fabricating devices from such a structure, and the devices fabricated from such a structure. In one embodiment, a first metal layer is carried by a substrate. A first sacrificial layer is carried by the first metal layer. A second metal layer is carried by the sacrificial layer. The second metal layer has a portion forming a micro-machined metal mesh. When the portion of the first sacrificial layer in the area of the micro-machined metal mesh is removed, the micro-machined metal mesh is released and suspended above the first metal layer a height determined by the thickness of the first sacrificial layer. The structure may be varied by providing a base layer of sacrificial material between the surface of the substrate and the first metal layer.

Abstract: A process comprises reducing the thickness of a substrate carrying a plurality of devices, with at least certain of the devices having a micro-machined mesh. A carrier wafer is attached to the back side of the substrate and the fabrication of the devices is completed from the top side of the substrate. Thereafter the plurality of devices is singulated. Various alternative embodiments are disclosed which demonstrate that the thinning of the wafer may occur at different times during the process of fabricating the MEMS devices such as before the mesh is formed or after the mesh is formed. Additionally, the use of carrier wafers to support the thinned wafer enables process steps to be carried out on the side opposite from the side having the carrier wafer. The various alternative embodiments demonstrate that the side carrying the carrier wafer can be varied throughout the process.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A method comprising reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device and ignoring said certain address bits before inputting at least one n-bit word into said memory array. The method may additionally comprise examining at least two of the least significant bits of a column address and wherein said reordering is responsive to said examining step. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA0-CA2 identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA0-CA2 being “don't care” bits assumed to be 000.

Abstract: The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.

Abstract: An integrated circuit testing apparatus having at least two of a test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: An aluminum container is comprised of a base portion, a substantially vertical wall portion extending upwardly from the base portion, a transition portion extending from the wall portion, and a neck portion extending from the transition portion. The neck portion is tapered and has an upper end having a wall thickness that is preferably less than the thickness of the wall of the remainder of the neck portion. The upper end of the neck portion may also be chamfered. The aluminum container of the present invention may be combined with a threaded sleeve to form a receptacle. The sleeve has an outer surface and an inner surface. The outer surface has threads thereon and the inner surface has a taper complementary to the taper of the neck portion so as to form a friction fit with the neck portion. The sleeve may also have a notch formed in the periphery of its upper outside surface.

Abstract: This invention provides a method of irreversibly immobilizing an enzyme into polyurethane coatings. This invention also provides for an enzyme-containing coating having a degree of immobilization of the enzyme of approximately 100%. The synthesis of waterborne polyurethane coatings in the presence of enzyme has enabled the irreversible attachment of the enzyme to the polymeric matrix. The distribution of immobilized enzyme as well as activity retention are homogeneous within the coating. Decreasing ECC hydrophobicity, via the use of a less hydrophobic polyisocyanate prepolymer during polymerization, significantly enhanced the intrinsic activity of the ECC.

Abstract: A method and apparatus of identifying the source of materials in a video sequence is disclosed. A series of pseudo frames is formed, for example by interleaving, from fields in adjacent frames. A correlation value is calculated for each of the pseudo frames. The correlation value may be a sum of absolute difference (SAD) of luminance values of every neighboring scan line accumulated over the entire pseudo frame. Scene changes may be determined, for example, based on the correlation values. Frames and repeated fields are identified based on the correlation values and the scene changes. Finally, the source of each frame in the series is identified based on the identification of frames and repeated fields.

Abstract: A method of operating a dispensing cabinet to identify the locations where items to be dispensed are located is comprised of a login step in which user information is entered into a processor controlling the dispensing cabinet. The processor unlocks certain doors of the dispensing cabinet in response to the user information. Assuming that a locate mode of operation has been chosen, the locations of the items to be located are determined by the processor. An alpha-numeric display positioned on a shelf within the cabinet begins flashing with the number of items to be located that are held by that shelf. After the user identifies the shelves having flashing alpha-numeric displays, the user may enter a dispense mode or may logoff causing the unlocked doors to lock.

Abstract: A chuck assembly comprises a housing defining a longitudinal axis and having a first end. A plurality of pins extend substantially parallel with the axis from the first end. The plurality of pins is located at a first radius relative to the axis. At least one of the pins is operable to move from the first radius to a second radius, relative to the axis. The chuck assembly also includes a means for moving at least one pin between the first radius and the second radius. A prime mover provides the necessary drive to the means for moving. The chuck assembly may be used in combination with various other components to form combinations or systems.

Abstract: The present invention is directed to a method and apparatus for providing variable output drive capability to an output driver. One aspect of the present invention is related to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output amplifier. The signal is used to enable certain of the pre-driver output stages in each output path. Another aspect of the present invention is related to a method of correcting output skews in a subsequent amplification stage. Other aspects of the present invention relate to a portion of a data path, a memory device, and a computer system all having a pre-driver with pre-driver output transistors responsive to signals indicative of the strength of output drive transistors.

Abstract: A slice plane, oriented parallel to a viewing plane, is passed through a cuboidal dataset at regular intervals. The intersection of the slice plane with the cuboidal volume dataset results in primitives (quads, triangles, etc. depending on the angle and position of the intersection) whose vertices have position coordinates (xu, yu, zu) and 3D-texture coordinates (r, s, t). The resulting primitives are rasterized using, for example, a traditional 3D graphics pipeline wherein the 3D-texture coordinates are interpolated across the scanlines producing 3D-texture coordinates for each fragment. The resulting 3D-texture coordinates for each fragment are stored in a 2D-texture storage area. These 2D-textures are called density-textures. By preprocessing the cuboidal dataset, the rendering process becomes a compositing process. A rendering process is comprised of looking-up, for each densel in the texture, the corresponding color and opacity values in the current lookup-table.

Abstract: A will call system for automating the management of storage and retrieval of items, preferably medical prescriptions. The automated system provides information control of all items in the system. The automated will call monitors the length of time an item remains in the system, and into which location an item is placed. An article sensor provides absolute confirmation that an item has been placed or removed from a designated location in the storage units. The automated will call system uses a controller to permit users to monitor and optimize the storage and retrieval procedures.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A carousel used in a restocking system is comprised of a drive track. A plurality of bins are arranged into rows, with the rows being driven by said drive track. A drive mechanism, e.g. an electric motor, drives the drive track. A sensor is provided to sense the position of the rows of bins. A processor is responsive to the sensor and data representative of a plurality of picks for more than one order for controlling the drive mechanism. By combining picks from different orders into a batch, the time spent driving the rows and time between picks is minimized. The carousel may be divided into a plurality of columns, each with its own drive track, drive mechanism, and sensor, to enable several rows to be brought into a pick position simultaneously.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.