Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: An acoustic transducer comprising a substrate; and a diaphragm formed by depositing a micromachined membrane onto the substrate. The diaphragm is formed as a single silicon chip using a CMOS MEMS (microelectromechanical systems) semiconductor fabrication process. The curling of the diaphragm during fabrication is reduced by depositing the micromachined membrane for the diaphragm in a serpentine-spring configuration with alternating longer and shorter arms. As a microspeaker, the acoustic transducer of the present invention converts a digital audio input signal directly into a sound wave, resulting in a very high quality sound reproduction at a lower cost of production in comparison to conventional acoustic transducers. The micromachined diaphragm may also be used in microphone applications.

Abstract: The present invention relates to a method for pre-characterizing a timing delay curve of a first current component, wherein the timing delay curve has a first curvilinear region and a second, linear method includes determining a first delay equation representing the first, curvilinear region of the delay curve, determining a second delay equation representing the second, linear region of the delay curve, and determining a corner capacitance representing a transition point from the first, curvilinear region to the second, linear region. The present invention further relates to a method of determining a scaling factor and applying the scaling factor to a pre-characterized base component to characterize the timing delay curve of additional circuit components.

Abstract: The invention relates to a method for measuring the effects of on-chin noise on signal propagation comprising measuring an inactive operating frequency of a first test circuit having a first plurality of elements connected by a first plurality of traces, measuring an inactive operating frequency of a second test circuit having a second plurality of elements connected by a second plurality of traces, measuring an inactive operating frequency of a third test circuit having a third plurality of elements connected by a third plurality of traces, and measuring an inactive operating frequency of a fourth test circuit having a fourth plurality of elements connected by a fourth plurality of traces, wherein the inactive operating frequencies of the first second, third, and fourth test circuits represent one or more effects of on-chin noise on signal propagation.

Abstract: The present invention determines that an object is moving within a scene. At run time, the number of primitives used to represent the moving object is reduced. The degree of reduction can be related to the amount of motion, i.e. speed, of the moving object. The moving object is then rendered based on the reduced number of primitives saving time and memory bandwidth.

Abstract: The invention relates to an apparatus for dynamically testing an integrated circuit having a core logic area. The apparatus comprises a first test circuit having a first plurality of elements connected by a first plurality of traces wherein the first test circuit mimics a data path within the integrated circuit, a second test circuit having a second plurality of elements connected by a second plurality of traces wherein the second plurality of traces are routed within the core logic area, a third test circuit having a third plurality of elements connected by a third plurality of traces wherein the third plurality of elements are randomly located within the core logic area, and a fourth test circuit having a fourth plurality of elements connected by a fourth plurality of traces wherein the fourth test circuit mimics a data path within the integrated circuit.

Abstract: One aspect of the present invention relates to a digitally controlled resistance standard, comprising a control system, a resistor element, hermetically sealed within an element assembly, a temperature/frequency measuring circuit for measuring the temperature of the resistor element and the frequency of an input signal, a heating/cooling assembly for raising and lowering the temperature of the resistor element a temperature controller for controlling the heating/cooling assembly, and a control system having a CPU. The control system is operable to execute computer instructions for storing the baseline characteristics of the resistor element, retrieve the temperature of the resistor element from the temperature/frequency measuring circuit, determine the actual resistance value of the resistor element, and adjust the actual resistance value of the resistor element to match a target resistance value using the temperature controller. A method for improving the accuracy of a resistance standard is also given.

Abstract: The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

Abstract: The present invention provides for a ladder carrying device that can be used to carry a ladder either over or under a carrier's shoulder. The ladder carrying device of the present invention can be mounted in a variety of different positions on the side rails and/or rungs of a ladder, thereby allowing the ladder carrying device to be positioned according to the carrier's preference.

Abstract: The invention relates to an integrated circuit, comprising a core logic area having a plurality of components therein, a first test circuit constructed to mimic a data path within the core logic area, a second test circuit constructed with a plurality of traces routed within the core logic area, a third test circuit constructed with a plurality of elements randomly placed within the core logic area, and a fourth test circuit constructed to mimic a data path within the core logic area, the fourth test circuit sharing a power source with at least one of the plurality of components within the core logic area. Each of the test circuits is operable to produce one or more signals for analyzing the effects of on-chip noise on signal propagation.

Abstract: The invention relates to a combination for determining the effects of signal noise and cross-talk on on-chip propagation, comprising an integrated circuit, and a testing system having a signal generator, a plurality of ring oscillators responsive to the signal generator and a signal analyzer responsive to the plurality of ring oscillators for dynamically measuring the effects of noise and cross-talk on the integrated circuit. The plurality of ring oscillators includes a first ring oscillator constructed to mimic a data path within the integrated circuit, a second ring oscillator constructed with traces routed within the core logic area, a third ring oscillator randomly placed within the core logic area, and a fourth ring oscillator constructed to mimic a data path within the integrated circuit, the fourth ring oscillator sharing a power source with at least one component of the plurality of components within the core logic area.

Abstract: A drawer for use in a dispensing cabinet is comprised of a tray movable between an open position and a closed position. An insert, approximately the length of the tray, is carried by the tray and defines the volume of the drawer. A lockable or sealable lid is carried by the insert. A release mechanism is provided to connect the insert to the tray in a manner that allows the insert to be easily disconnected from the tray. Removal of the insert enables inserts to be swapped so that inserts from which inventory has been depleted can be replaced with stocked inserts. A dispensing cabinet and a method of restocking the cabinet are also disclosed.

Abstract: An aluminum container is comprised of a base portion, a substantially vertical wall portion extending upwardly from the base portion, a transition portion extending from the wall portion, and a neck portion extending from the transition portion. The neck portion is tapered and has an upper end having a wall thickness that is preferably less than the thickness of the wall of the remainder of the neck portion. The upper end of the neck portion may also be chamfered. The aluminum container of the present invention may be combined with a threaded sleeve to form a receptacle. The sleeve has an outer surface and an inner surface. The outer surface has threads thereon and the inner surface has a taper complementary to the taper of the neck portion so as to form a friction fit with the neck portion. The sleeve may also have a notch formed in the periphery of its upper outside surface.

Abstract: A phase detector is comprised of two cross-coupled gates which are capable of phase discrimination down to a level of approximately 10 picoseconds. An arbiter circuit, responsive to the cross-coupled gates, generates mutually exclusive UP and DOWN pulse signals. The UP and DOWN pulse signals may be filtered and used to control the delay line of an all digital delay locked or phase locked loop. Methods of operation are also disclosed.

Abstract: An addressing scheme and associated hardware allows for two different types of access, one for reading and one for writing, to take place. A memory device constructed according to the invention comprises a plurality of arrays of memory cells. Peripheral devices are provided for reading information out of and for writing information into the plurality of memory cells. The peripheral devices include a reorder circuit responsive to certain address bits for ordering bits received from the plurality of arrays and an address sequencer for routing certain of the address bits to the reorder circuit during a read operation. The method of the present invention comprises reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device.

Abstract: A pill dispensing system includes a shelving unit in array form that holds a number of bulk containers, each holding a bulk amount of a pill to be dispensed. A computer controlled robot removes a selected bulk container and places it on a counter that also dispenses pills. The robot has an arm with a free end portion that can grip a bulk container or a single pill bottle to be filled. The robot is computer controlled to retrieve an empty pill bottle, place it on a label printing and applying unit, then place it next to the counter/dispenser to receive the selected number of selected prescription pills, then place the filled, labeled bottle on a conveyor. In an alternate embodiment, pill bottles are dispensed from a dispenser that holds bottles on inclined plates and feeds them to a vertical dispensing channel. Gates prevent the flow of bottles from an inclined position until the plate above has been emptied.

Abstract: A memory device is comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. The peripheral devices include a decode circuit responsive to a first portion of address information for identifying an address and is further responsive to a second portion of the address information for identifying an order. The address may be a read address or a write address, and the order may be the order for reading data or writing data, respectively. The peripheral devices may also include a read sequencer circuit or both a write sequencer circuit and a read sequencer circuit for reordering bits to be read or written in response to another portion of the address information. Methods of operating such a memory device including outputting or reading a word from a memory array in two prefetch steps or operations are also disclosed.

Abstract: One aspect of the present invention relates to a voltage pump for an integrated circuit, comprising a plurality of voltage pump circuits operable in response to a clock signal input thereto, the plurality of voltage pump circuits being divided into a plurality of groups for operation in response to an enable signal produced by the integrated circuit in either separate or concurrent operating modes to achieve predetermined levels of power output, an oscillator circuit for producing the clock signal, first and second regulator circuits for producing first and second signals, respectively, for controlling the oscillator circuit, and a regulator select circuit for selecting one of the first and second signals for input to the oscillator. Other aspects and benefits of the invention are also described herein.

Abstract: A chuck assembly comprises a housing defining a longitudinal axis and having a first end. A plurality of pins extend substantially parallel with the axis from the first end. The plurality of pins is located at a first radius relative to the axis. At least one of the pins is operable to move from the first radius to a second radius, relative to the axis. The chuck assembly also includes a means for moving at least one pin between the first radius and the second radius. A prime mover provides the necessary drive to the means for moving. The chuck assembly may be used in combination with various other components to form combinations or systems. A method of labeling a container is also disclosed.

Abstract: The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst clock. Command capture logic receives command information in response to the system clock. A storage element is responsive to the command capture logic for storing certain command information such as write commands. A two stage pipeline receives the command information from the storage element in response to the burst clock and outputs the command information in response to the system clock. Methods of operating the apparatus are also disclosed.