Abstract: A process for controlling focus parameters in a lithographic process used in manufacture of microelectronic circuits. The process comprises initially providing a lithographic mask having a target mask portion containing a measurable dimension sensitive to defocus, projecting an energy beam through the target mask portion onto a first location of a substrate at a first focus setting, and lithographically forming a first target on the substrate corresponding to the first focus setting, the first target containing a measurable dimension sensitive to defocus. The process then includes projecting an energy beam through the target mask portion onto a second location of the substrate at a second focus setting, lithographically forming a second target on the substrate corresponding to the second focus setting, the second target containing a measurable dimension sensitive to defocus, and measuring the defocus sensitive dimension for each of the first and second targets on the substrate.

Abstract: A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.

Abstract: A method and computer program product is described for displaying files associated with multiple hypertext links selected from a Web page. A user selects a set of links from a Web page that contains multiple links, and the linked files are displayed in a preferred sequence without having to repeatedly return to the original Web page. In addition, files associated with these links can be downloaded while the first links are being displayed and viewed by the user. Thus, both the usability and the performance in Web browsing is improved.

Abstract: A method for image reversal in semiconductor processing includes forming a first implant mask layer upon a semiconductor substrate and forming a patterned photoresist layer over the first implant mask layer. Portions of the first implant mask layer not covered by the patterned photoresist layer are removed so as to expose non-patterned portions of the substrate. The photoresist layer is then removed, and a second implant mask layer is formed over the non-patterned portions of the substrate, wherein the first implant mask layer has an etch selectivity with respect to the second implant mask layer. The remaining portions of the first implant mask layer are removed to expose a reverse image of the substrate, including initially patterned portions of the substrate.

Abstract: A method of evaluating process effects of multiple exposure photolithographic processes by first determining a set of expected images for each exposure step or process of the multiple exposure process individually and then obtaining a composite set of images by sequentially perturbing images from a first or previous exposure step by weighted images from the subsequent exposure step. Preferably, the expected images are determined by simulation in the form of normalized aerial images over a range of defocus for each exposure step, and the weighting factor used is the dose-ratio of the subsequent exposure dose to the prior step exposure dose. The resulting composite set of images may be used to evaluate multiple exposure processes, for example, to provide an estimate of yield for a given budget of dose and focus errors, or alternatively, to provide specifications for tool error budgets required to obtain a target yield.

Abstract: A method of transmitting data from a host computer to a portable information device is disclosed. Optical pulses are displayed by illuminating an area of pixels, or optical zone, on a display monitor. Time series of optical pulses are displayed, including a bit stream that provides clocking information displayed within an optical zone concurrently with a data bit stream encoded using a standard encoding scheme (such as a serial or parallel transmission scheme or a combination thereof), and then detecting and downloading the bit stream data by using a suitably configured sensing device connected to a portable information device. If the display monitor is a color display monitor, brightness of each primary color may be used as an independent transmission channel. In addition, multiple optical zones may be used to transmit data, which allows the present invention to be used with monochrome display monitors.

Abstract: A method is described for designing an alternating phase shifted mask (altPSM) by optimally selecting the width of phase shapes. The selection of optimal phase shape widths is achieved by providing a lithography metric that describes the relationship between phase shape width and the target image dimension such that the metric, such as process window or across chip linewidth variation (ACLV), is optimized. In a preferred embodiment, ACLV is computed by Monte Carlo simulation by providing a set of error distributions for lithographic parameters such as focus, dose, lens aberrations, and the like. Alternatively, a lookup table of optimal phase widths associated with target image dimensions may be provided. The resulting altPSM is characterized by phase shapes having widths that vary according to the widths of the target image dimensions.

Abstract: A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.

Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Abstract: A sensing circuit for performing a direct read of a DRAM memory cell by using a high transfer ratio and a single ended read of a single bitline, wherein a limited number of memory cells are connected to the single bitline to limit the capacitance thereof to provide the high transfer ration. The direct read circuit includes four transistor devices, with three devices preferentially being nFETs. The direct read circuit provides a self-timed write back of data to a memory cell after the data is destructively read from the memory cell in a read operation, provides significant electrical power savings relative to prior art read circuits, as a read operation of a data 0 does not utilize any significant electrical power, and in a folded bitline architecture provides improved noise immunity as each non-active bitline shields an adjacent active bitline.

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

Abstract: A method and structure for increasing the area and capacitance of both trench and planar integrated circuit capacitors uses Si nodules deposited on a thin dielectric seeding layer that is absorbed during subsequent thermal processing, thereby avoiding a high resistance layer in the capacitor.

Abstract: A method for manufacturing a semiconductor chip which has transistors is disclosed. The transistors include first type transistors which have a first type of doping and second type transistors which have a second type of doping different than the first type of doping. The method includes forming a conductive layer on a substrate. The conductive layer includes first regions that have the first type of doping and second regions have the second type of doping. The invention patterns a mask over the conductive layer, and the mask protects portions of the conductive layer where gate conductors will be located. Next, the invention partially etches unprotected portions of the conductive layer. The partially etching process allows a layer of the unprotected portions to remain, such that the substrate is not exposed by the partially etching process.

Abstract: A method and arrangement of obtaining a transparent image of a resist contact hole or feature provided on a silicon wafer through a scanning electron microscope (SEM), with an absence of deforming the feature, such as the contact hole. In particular, the method is directed to the obtaining of a transparent image of a resist contact hole or feature by SEM without damaging the silicon wafer.

Abstract: A method and structure for the electrical characterization of a semiconductor device comprising, first, forming a hole having a diameter less than 0.15 &mgr;m, wherein the hole is created using focused ion beam (FIB) etching, and through at least a protective cap layer formed over the device. The FIB etching occurs in an electron mode using a beam current less than 35 &rgr;A with an aperture size less than 50 &mgr;m, and at an acceleration voltage of about 50 kV. Second, the surface of the hole is coated with a metal, preferably using chemical vapor deposition (CVD) and preferably using a FIB device. Third, a metal pad is deposited, preferably by FIB CVD, over the hole. Fourth, the pad is probed to determine characteristics and/or detect defects of the electrical device. The present invention allows for electrical characterization without causing damage to the device or its features.

Abstract: A method of forming openings on a semiconductor wafer comprising an initial step of providing a first film layer over the semiconductor wafer. A first opening in the first film layer is created by transferring an image of the first opening from a photoresist layer into the first film layer using an etching procedure. The first opening includes horizontal and vertical surfaces and has first width and height dimensions. After removing the photoresist layer, a second film layer is deposited over the first film layer and the opening such that the opening has a second width and height dimension which is less than the first width and height dimension. The second film layer is then anisotropically etched from the horizontal surface of the first film layer, and the horizontal surface of the opening such that the opening includes the first height dimension and the second width dimension.

Abstract: Disclosed herein is a method of filling isolation trenches in a substrate. The method includes anisotropically etching trenches in a surface of a substrate and partially filling the trenches with a deposited oxide. As a consequence of the deposition, the oxide accumulates in mounds on the surface between trenches. The trenches are then filled with a supporting material of a highly flowable material such as anti-reflective coating (ARC), low-K dielectric, or a spin-on-polymer, or alternatively, a supporting material of polysilicon. A flattening process is then applied to lower the mound topography. The supporting material is then removed and the filling of the trenches with oxide is then continued. When polysilicon is used as the supporting material, the mounds are removed by wet etching prior to removing the polysilicon.

Abstract: A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.

Abstract: A method for generating an optical proximity correction (OPC) model includes generating a set of correction rules for a wafer design containing at least one of lines and assist features, determining a set of corrections that need to be made over a range of sizes and spaces of the lines and assist features based on the set of correction rules, and creating an optical proximity correction model for correcting the wafer design based on the set of corrections.

Abstract: A method for employing a plurality of reusable reticles in an integrated circuit manufacturing process employing lithographic exposure of a semiconductor wafer. Initially there is provided a matrix of a plurality of reticles, each matrix comprising a plurality of tuples of reticles, each reticle tuple comprising one or more reticles. The method then includes defining at least one set of valid groups of reticles in the matrix for use in a desired lithographic exposure process, defining a set of conditions for determining availability of all reticles in the valid groups in the lithographic exposure process, and comparing the availability conditions to the reticles in the set of valid groups and eliminating valid groups which do not meet the availability conditions, leaving non-eliminated valid groups.