Abstract: An apparatus and method is described for cleaning semiconductor wafers using a dilute aqueous solution including at least 80% deionized water, sulfuric acid, an oxidant such as hydrogen peroxide, and a small amount of hydrofluoric acid (HF), preferably in the range of about 5 ppm to about 12 ppm. The automated system mixes the water, sulfuric acid, hydrogen peroxide, and HF to form a cleaning solution having a target HF concentration within the preferred range, for example at 8 ppm. Subsequently, the system maintains the HF concentration at least within about 0.5 ppm to about 1 ppm of the target HF concentration. Thus the system allows effective and predictable cleaning of semiconductor wafers while minimizing damage to metal features, and minimizing cost and waste disposal impacts.

Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent ref lows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by means of a screening mask. Interconnect structures are then bonded to the I/O pad.

Abstract: A monitoring system is described for monitoring gas delivery systems from a Web browser. The system collects data generated from existing gas delivery systems, as well as other information, such as maintenance and repair data, and stores the data in a database located on a centralized server computer system. An authorized user may access the database from a remote location, check the status of the gas cylinders, manifolds, and tools, and generate reports including mean-time-to-failure reports, serviceability, comparisons among buildings or sites, thus saving time and helping to minimize future downtime of the gas delivery system. In addition, the monitoring system automatically monitors the gas delivery system for critical conditions and automatically notifies appropriate personnel of conditions that require immediate attention.

Abstract: A compact DRAM cell array that substantially minimizes floating-body effects and device-to-device interactions is disclosed. The compact DRAM cell array includes a plurality of annular memory cells that are arranged in rows and columns. Each annular memory cell includes a vertical MOSFET and an underlying capacitor that are in electrical contact to each other through a buried-strap outdiffusion region which is present within a portion of a wall of each annular memory cell such that the portion partially encircles the wall. The remaining portions of the wall of each annular memory cell have a body contact region that serves to electrically connect the annular memory cell to an adjacent array well region. The DRAM cell array also includes a plurality of wordlines overlaying the vertical MOSFETs, and a plurality of bitlines that are orthogonal to the plurality of wordlines.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.

Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Abstract: A system and method is described for lithographically printing patterns on a semiconductor using combinations of illumination and mask patterns which are optimized together to produce the desired pattern. The method of optimizing both illumination and mask pattern allows the development of mask patterns that are not constrained by the geometry of the desired pattern to be printed. Thus, the method provides high quality images even when the desired printed patterns have critical dimensions that approach the resolution limits of a lithographic system. The resulting mask patterns using the method do not obviously correspond to the desired patterns to be printed. Such masks may include phase-shifting technology that use destructive interference to define dark areas of the image and are not constrained to conform to the desired printed pattern.

Abstract: A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap.

Abstract: Optical proximity correction (OPC) and assist feature rules are generated using a process window (PW) analysis. A reference pitch is chosen and the mask bias is found that optimizes the process window. This can be done using standard process window analysis or through a weighted process window (WPW) analysis which accounts for focus and dose distributions that are expected in a real process. The WPW analysis gives not only the optimum mask bias, but also the center focus and dose conditions for the optimum process centering. A series of other pitches and mask biases are then analyzed by finding the common process window with the reference pitch. For the standard PW analysis, a common process window is found. For the WPW analysis, the WPW is computed at the center focus and dose conditions found for the reference pitch. If mask or lens errors are to be accounted for, then multiple structures can be included in the analysis.

Abstract: A semiconductor structure (and method for manufacturing the same) comprises an active array of first elements having a first manufacturing precision, a peripheral region surrounding the active array, the peripheral region including second elements having a second manufacturing precision less than the first manufacturing precision, wherein the second elements are isolated from the active array and comprise passive devices for improving operations of the active array.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.

Abstract: The present invention relates generally to a new method and apparatus to enable high yielding double sided and/or multipass screening in the manufacture of multilayer ceramic packages. Also, the present invention enables the screened features to be buried partially or fully with flat surface being available for high yielding post-sinter operations.

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Abstract: A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

Abstract: A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.

Abstract: An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.