Patents Represented by Attorney, Agent or Law Firm Victor M. Genco, Jr.
  • Patent number: 6015722
    Abstract: The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: January 18, 2000
    Assignee: Gore Enterprise Holdings, Inc.
    Inventors: Donald R. Banks, Ronald G. Pofahl, Mark F. Sylvester, William G. Petefish, Paul J. Fischer
  • Patent number: 6014317
    Abstract: A chip package is provided for controlling warp of electronic assemblies. The chip package has a first component mounted on one side of a substrate. The substrate is a multi-layered laminate having a plurality of dielectric layers made of an organic material. The first component has a different coefficient of thermal expansion (CTE) than the substrate. The chip package includes a second component mounted on an opposite side of the substrate in a location substantially opposite the first component. The second component has a CTE that approximately matches the CTE of the first component. The second component tends to generate bending moments that offset distorting bending moments that may otherwise exist in the chip package without the second component.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: January 11, 2000
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: Mark F. Sylvester
  • Patent number: 6011697
    Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: January 4, 2000
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: John J. Budnaitis, Paul J. Fischer, David A. Hanson, David B. Noddin, Mark F. Sylvester, William George Petefish
  • Patent number: 5983974
    Abstract: A lid for a chip/package system includes a body sized to fit over an integrated circuit chip and being connectable to a package. The body has at least two regions exhibiting different coefficients of thermal expansion, with one CTE matching that of the chip and the other matching that of the package.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: November 16, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: Mark F. Sylvester
  • Patent number: 5985686
    Abstract: In the fabrication of vertical cavity surface emitting lasers, patterned wafer fusion promotes low-loss refractive index guiding combined with a mechanically robust and reproducibly fabricatable structure. A fabricated laterally refractive index guided VCSEL includes a plurality of layers of semiconductor, including a bottom mirror stack disposed above a semiconductor substrate, an active region having upper and lower claddings sandwiching a layer of quantum wells disposed above the bottom mirror stack, and a top mirror stack disposed above the active region. A recessed pattern is etched in one of the plurality of layers to create a mode confining layer, prior to wafer fusion, which forms a buried air gap subsequent to wafer fusion. The buried air gap provides a lateral refractive index profile, which functions as a low-loss means for index guiding the VCSEL optical energy to the single fundamental transverse mode.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: November 16, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: Vijaysekhar Jayaraman
  • Patent number: 5976974
    Abstract: In a method for forming redundant signal traces and corresponding electronic components, a photoresist pattern which defines a semi-additive signal image is coated on at least one first conductive layer of a composite base substrate. A barrier layer of etch-resistant metal is deposited on the first conductive layer. The photoresist is removed, thereby forming a first barrier signal trace having a first line width. Optionally, one or more vias may be formed in the substrate. A surface conductive layer is deposited on the first conductive layer, the barrier layer, and on a surface of the optional vias. A photoresist pattern is coated on the surface conductive layer which defines a subtractive signal image. Predetermined portions of the surface conductive layer and the first conductive layer are removed. The photoresist is removed forming a second signal trace in overlying relationship with the first barrier signal trace and having a second line width greater than the first line width.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: November 2, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Paul J. Fischer, Robin E. Gorrell
  • Patent number: 5973290
    Abstract: A laser via drilling system, and method of operation thereof, operates at an increased pulse repetition rate, but provides output pulses of sufficient energy and consistent pulse to pulse energy. In order to drill a via hole in a substrate, a pulsed laser beam is formed using a lithium triborate (LiB.sub.3 O.sub.5) crystal for harmonic generation. The laser beam has an energy density that is greater than an ablation threshold of the substrate. A via hole is formed using the pulsed laser beam. The energy density of the pulsed laser beam is decreased to an energy density that is less than the first energy density and is less than the ablation threshold of the substrate. The pulsed laser beam is re-positioned to a site of a next via to be formed. The energy density of the pulsed laser beam is increased back to the original energy density and a next via hole is formed. The energy density of the pulsed laser beam is decreased by increasing the pulse repetition rate of the beam.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: October 26, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: David B. Noddin
  • Patent number: 5970319
    Abstract: The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: October 19, 1999
    Assignee: Gore Enterprise Holdings, Inc.
    Inventors: Donald R. Banks, Ronald G. Pofahl, Mark F. Sylvester, William G. Petefish, Paul J. Fischer
  • Patent number: 5965043
    Abstract: A method of forming a via in a laminated substrate by forming ablated material by laser drilling a via in a laminated substrate. The ablated material is deposited on a sidewall of the via. An ultrasonic treatment is applied to the drilled substrate thereby removing ablated material redeposited on sidewalls of the via.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: October 12, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: David B. Noddin, Robin E. Gorrell, Michael R. Leaf
  • Patent number: 5966593
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: October 12, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: John J. Budnaitis, Jimmy Leong
  • Patent number: 5966022
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: October 12, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: John J. Budnaitis, Jimmy Leong
  • Patent number: 5945217
    Abstract: A thermally conductive composite article is provided having a PTFE material or a PTFE matrix material which has disposed therein thermally conductive particles, and a phase change material.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: August 31, 1999
    Assignee: Gore Enterprise Holdings, Inc.
    Inventor: James R. Hanrahan
  • Patent number: 5928791
    Abstract: The present invention relates to a method of rapidly cooling a sintered coherent film formed from PTFE, by quenching or other suitable cooling technique, which results in a PTFE film, that has improved dielectric properties, such as, increased breakdown voltage and lower current leakage, and the resulting article.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: July 27, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: C. Thomas Rosenmayer
  • Patent number: 5919329
    Abstract: The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: July 6, 1999
    Assignee: Gore Enterprise Holdings, Inc.
    Inventors: Donald R. Banks, Ronald G. Pofahl, Mark F. Sylvester, William G. Petefish, Paul J. Fischer
  • Patent number: 5920671
    Abstract: An improved cable assembly is provided having a signal transmission core. A first jacket is disposed about the signal transmission core. A first strength member array is disposed about the first jacket. The strength member array is defined by at least two synthetic fibrous strength members which are each comprised of a plurality of filaments. Each strength member is disposed within an individual friction reducing layer. A second jacket is disposed about the strength member array.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: July 6, 1999
    Assignee: Gore Enterprise Holdings, Inc.
    Inventor: John David Smith
  • Patent number: 5918108
    Abstract: A vertical cavity surface emitting laser is constructed on a semiconductor substrate, and includes a second mirror stack disposed on the substrate, a gain region with an active material within the second mirror stack capable of emitting electromagnetic radiation at a fundamental wavelength, a non-linear element disposed above the second mirror stack capable of emitting electromagnetic radiation at a harmonic of the fundamental wavelength in response to the electromagnetic radiation at the fundamental wavelength, and a first mirror stack disposed above the non-linear element. Electrodes are applied to the second mirror stack and the substrate for electrically pumping current into the gain region without passing through the non-linear element. A conducting layer can be disposed in the second mirror stack and an annular current confinement region can be formed in the second mirror stack around the gain region to help guide current into the active material.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: June 29, 1999
    Assignee: W. L. Gore & Associates, Inc
    Inventor: Frank H. Peters
  • Patent number: 5914976
    Abstract: An optoelectronic module includes one or more VCSEL transmitters and/or photodetectors coincidentally aligned along a common central longitudinal axis. Differing wavelengths of light can be received and transmitted by the optoelectronic module optically coupled to a single optical fiber or in a free-space link. The optoelectronic module is able to receive two wavelengths and transmit one wavelength, or can transmit two wavelengths in the optical link. The VCSEL transmitter can be optically pumped by a vertically integrated pump VCSEL. A parallel optical link supports transmission and reception for each duplex channel on a single optical fiber.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: June 22, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Vijaysekhar Jayaraman, David J. Welch
  • Patent number: 5910354
    Abstract: A metallurgical interconnect composite is provided defined by a compliant, metallurgical, open cell, porous substrate which has a plurality of Z-axis conductive pathways extending from one side of the substrate to the other side. Each conductive pathway terminates in a solder covered surface area.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: June 8, 1999
    Assignee: W.L. Gore & Associates, Inc.
    Inventors: Carmine G. Meola, Daniel D. Johnson, Donald R. Banks, Joseph G. Ameen
  • Patent number: 5910255
    Abstract: A method for forming a blind-via in a laminated substrate by laser drilling a blind-via from a top surface of the substrate toward a bottom surface of the substrate using a first laser and a first trepanning motion of a laser focal spot of the first laser. Then, the via is laser drilled from the top surface toward the bottom surface using a second laser and a second trepanning motion of a laser focal spot of the second laser.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: June 8, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: David B. Noddin
  • Patent number: D412043
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: July 13, 1999
    Assignee: Gore Enterprise Holdings, Inc.
    Inventors: John W. Dolan, Brad F. Abrams, Robert M. Russell, David D. McClanahan