Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

Abstract: A method and apparatus is provided for dimensioning and manipulating a patterned material by selectively applying a vacuum and/or positive pressure to the patterned material.

Abstract: An electrically conductive composite article is provided having a polytetrafluoroethylene fibril matrix and a predetermined volume. The electrically conductive composite article comprises electrically conductive particles, and electrically nonconductive, energy expanded hollow polymeric particles. The volume percent of the electrically conductive particles is at least 20 volume percent. The electrically conductive composite article is continuously electrically conductive throughout its entire structure. Accordingly, electric current freely flows through the composite article due to the low resistivity of the article. The electrically conductive composite article may additionally include an elastomer material disposed within the article in a discontinuous fashion.

Abstract: A package for mounting an integrated circuit chip includes a body having at least a first region and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.

Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

Abstract: A low dielectric constant material is provided for use as an insulation element in an electronic device, such as but not limited to an integrated circuit structure for example. Such a low dielectric constant material may be formed from an aqueous fluoropolymer microemulsion or microdispersion. The low dielectric constant material may be made porous, further lowering its dielectric constant. The low dielectric constant material may be deposited by a spin-coating process and patterned using reactive ion etching or other suitable techniques.

Abstract: A method of manufacturing a multi-layered structure includes forming first and second layers, patterning the first layer, determining a distribution of material in at least one area of the first layer, and altering the material content of one of the first and second layers in at least one of the first layer area and a corresponding area of the second layer to approximately match the material content of the first layer and second layers.

Abstract: The present invention relates to assembly techniques and the resulting products which are thermally stable, have high structural integrity, and compensate for thermal stresses that occur between the various components of the package. This is accomplished, in-part, by designing the package so that the coefficient of thermal expansion (CTE) of a stiffening ring which is mounted on the package substrate matches the CTE of the substrate and optional lid. Further, the particular adhesives used to bond the stiffening ring are chosen to match their CTE to that of the substrate, ring and lid. Moreover, the substrate is designed so that its CTE, at least in-part, matches that of the chip, and also that of the stiffening ring.

Abstract: The invention relates to an open cell, porous, selectively conductive member containing an elastomer that is reusable in use and preparation. The scaffold for the elastomer has conductive areas through conductive, z-axis pathways are provided which are electrically isolated from adjacent z-axis conductive pathways. The elastomer is non-adhesive and/or non tacky and allows for temporary connection of electronic components.

Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level bum-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

Abstract: A method and apparatus are provided for aligning and laminating stiffeners to substrates in electrical circuits. Generally, this method includes placing a substrate within an alignment frame or tool; applying an adhesive on the substrate; placing a stiffener on the adhesive to form a chip package; applying sufficient pressure and heat to the package for a sufficient time to cure the adhesive. Another method of the present invention includes placing a substrate within an alignment tool or frame; applying an adhesive on the substrate within the alignment tool; placing a stiffener on the adhesive to form a package; applying sufficient heat and pressure to the package for a sufficient time to tack the stiffener to the substrate; removing the package from the alignment tool or frame; and heating the package for a sufficient time and temperature to cure the adhesive wherein the stiffener enhances rigidity of the package.

Abstract: A method of making a laminated structure includes forming a first lamination having first and second conductive layers having inner and outer surfaces and being spaced apart by a dielectric layer, drilling through the first conductive layer and dielectric layer to form a blind via having a bottom coexistent with the inner surface of the second conductive layer, plating the blind via with a conductive material, and patterning the second conductive layer to form at least one contact pad over the blind via.

Abstract: A method of preparing an adhesive composite is provided where a fluoropolymer having nodes and interconnected fibrils with a void volume formed from the node and interconnected fibril structure is at least partially filled with a paste formed from a thermoset or thermoplastic adhesive and a particulate vapor phase formed inorganic filler having uniform surface curvature, sufficient adhesive and filler are present to provide a composite having between about 5 to about 40 volume percent polymeric substrate, 10-95 volume percent adhesive and filler imbibed within the voids of said substrate and 5 to 85 volume percent inorganic filler is contained within the composite. In the composite, the ratio of mean flow pore size to largest particle size is at least above 0.7; or the ratio of mean flow pore size to average particle size is greater than 1.5; or the ratio of minimum pore size to average particle size is at least above 0.8; or the ratio of minimum pore size to largest particle size is at least above 0.4.

Abstract: A vertical-cavity surface-emitting laser (VCSEL) has an active region, first and second mirror stacks forming a resonant cavity with a radial variation in index forming a transverse optical mode, and a thin insulating slot within the cavity to constrict the current to a diameter less than the beam waist of the optical mode thereby improving device efficiency and preferentially supporting single mode operation. In one embodiment, an insulating slot is formed by etching or selectively oxidizing a thin aluminum-containing semiconductor layer in towards the center of a cylindrical mesa. The slot thickness is sufficiently thin that the large index discontinuity has little effect on the transverse optical-mode pattern. The slot may be placed near an axial standing-wave null to minimize the perturbation of the index discontinuity and allow the use of thicker slots.

Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Abstract: A method and apparatus is provided for dimensioning and manipulating a patterned material by selectively applying a vacuum and/or positive pressure to the patterned material.

Abstract: A method of forming a via in a laminated substrate by placing a first mask between an output optics of a laser and an exposed surface of a laminated substrate. The first mask has a first aperture corresponding to a location of a via in the substrate. A second mask is placed between the first mask and the output optics of the laser. The second mask has a second aperture disposed within a main beam of a laser beam output from the laser and blocks side lobes of the laser beam from reaching the exposed surface of the substrate.

Abstract: A method of minimizing warp and die stress in the production of an electronic assembly includes connecting one surface of a die to a package, and connecting an opposite surface of the die to a lid disposed over a constraining ring that is mounted to the package. The lid has a size, shape and coefficient of thermal expansion (CTE) selected to generate a bending moment that opposes bending moments resulting from connecting the die to the package.

Abstract: A method for determining a fiducial misregistration of conductive layers of a laminated substrate by providing a plurality of alternatingly disposed dielectric layers and conductive layers. A predetermined area of resistive material is formed as part of at least one conductive layer. Each predetermined area of resistive material is formed at a same corresponding location in each respective conductive layer, and each predetermined area of resistive material has a first end and a second end. A through-via is formed and connected to each predetermined area of resistive material between the first and second ends of each respective predetermined area. A total resistance is determined between the first end and the second end of each predetermined area of resistive material. A first fractional resistance is determined between the first end of each predetermined area of resistive material and the through-via.

Abstract: A method and apparatus are provided for coining solder balls on an organic electrical circuit package. Generally, this method includes placing a slug on one or more of the solder balls; and applying sufficient pressure for a sufficient period of time on the slug to flatten the surface of the solder balls so as to form planar solder coins. The apparatus includes a press; a ram attached to the press; a platform for receiving the package and a slug placed upon the solder balls.