Abstract: Individual two-dimensional barcodes are provided for individual chips arrayed on a wafer, individual lead frames to each of which chips are bonded and individual packaged products constituted of resin sealed semiconductor chips based upon chip ID information, to enable information management to be implemented separately for individual chips, individual frames and individual chip products. Thus, a higher degree of efficiency and a higher degree of accuracy in the information management for semiconductor devices are achieved in all processes of semiconductor production including the individual manufacturing processes, the physical distribution process, the shipping process and the claim handling process.

Abstract: A voltage divider for dividing an input voltage includes a fixed resistor, a variable resistor, an input node and an output node. The fixed resistor has a fixed resistance value independent of an operating frequency, and includes at least one resistance device. The variable resistor has a variable resistance value that varies corresponding to a variation of the operating frequency. The input node receives the input voltage, and the output node outputs an output voltage, which includes the input voltage divided based on the fixed resistance value and the variable resistance value.

Abstract: A wiring structure includes a first insulation layer located on a substrate, and first and second plugs located on the substrate and extending through the first insulation layer. The first plug includes an upper peripheral portion that defines a recess and the second plug is adjacent to the first plug. A second insulation layer is located on the first insulation layer, the first plug and the second plug. A bit line structure is located on the second insulation layer and is electrically connected to the first plug. A protection spacer is located on the recess of the first plug and a sidewall of an opening in the second insulation layer. The opening exposes the recess of the first plug, the second plug and the sidewall of the bit line structure. A pad is located in the opening and contacts the second plug.

Abstract: A method for inspecting a semiconductor device includes carrying out a first test for inspecting characteristics of semiconductor devices under a shielded (dark) condition to discriminate non-defective devices; and carrying out a second test on the semiconductor devices which have passed the first test as non-defective devices, for inspecting characteristics of the semiconductor devices. The second test is carried out while a predetermined color of light is applied to the semiconductor devices.

Abstract: A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.

Abstract: Provided are a flash memory device and a method of driving the same for improving reliability of stored set information. The method of driving the flash memory device includes applying power to the flash memory device, the flash memory device having a memory cell array for storing set information regarding operation environment settings, where the set information includes at least one bit. The method further includes performing an initial read operation on the memory cell array and judging a status of data, corresponding to the set information, read during the initial read operation to determine whether the initial read operation has passed or failed. Each bit of the set information is extended to n bits (where n is an integer equal to or greater than 2). The n bits are respectively stored in different input/output regions in the memory cell array.

Abstract: A control signal for removal of an afterimage from an active matrix display device is generated after the removal or disconnect of power from the device. A detector circuit receives a first voltage from a first voltage source and a second voltage from a second voltage source, and outputs a detection signal when either one of the first and second voltages drops to a given voltage level. An output circuit which receives the detection signal and outputs the control signal for removal of the afterimage from the active matrix display device.

Abstract: A flash memory device includes at least two mats and a row decoder shared by the mats. Each mat includes multiple word lines, bit lines, and blocks that share the bit lines. The row decoder includes a block decoder that generates a block selection signal for selecting a block, a block word line boosting circuit that generates a high voltage block word line signal in response to the block selection signal, a word line driver that drives word line drive signals driving the word lines of the selected block using drive voltages according to an operation mode and the word lines of an unselected block using a first bias voltage, and a string selection line driver that drives a string selection signal of the selected block using a drive voltage according to the operation mode and the string selection signal of the unselected block using a second bias voltage.

Abstract: A clock generating apparatus includes a clock generator and a controllable delay line. The clock generator receives an external clock signal and generates multiple clock signals having different phases by delaying the external clock signal. The controllable delay line receives one of the multiple clock signals as a first clock signal and delays the first clock signal by a first interval in response to an externally applied control signal. The delayed first clock signal is input to the clock generator.

Abstract: A method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.

Abstract: A leadframe includes a die pad and a plurality of leads corresponding to the die pad. The die pad for supporting a die is formed with a plurality of sides, each of the sides having at least one recess portion and at least one protrusion portion. The leads are substantially coplanar to the die pad. The leads include a plurality of first leads and a plurality of second leads. The first leads extend into the recess portions respectively, and the second leads are aligned with the protrusion portions. The length of the first leads is greater than that of the second leads. The length of wires electrically connecting the die to the leads or the die pad can be adjusted by the sides of the leadframe with the recess portion and the protrusion portion having a dimension corresponding to the leads, so as to save the manufacture cost of the leadframe.

Abstract: A method for fabricating MOS-FET using a SOI substrate includes a process of ion implantation of an impurity into a channel region in a SOI layer; and a process of channel-annealing in a non-oxidized atmosphere. In the ion implantation process, a concentration peak of the impurity is made to exist in the SOI layer. Moreover in the channel-annealing process, the impurity is distributed with a high concentration in the vicinity of the surface of the SOI layer under the following condition with the anneal temperature as T (K) and annealing time as t (minutes): 506×1000/T?490<t<400×1000/T?386.

Abstract: A package and the method for making the same, and a stacked package, the method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement.

Abstract: A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an internal power voltage level. The switching unit transfers a first output of the first power driver to the word line driver in response to a first switching signal and transfers a second output of the second power driver to the word line driver in response to a second switching signal. The word line driver alternately drives a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal.

Abstract: A system and method of generating a test clock signal for scan testing of a main circuit in a semiconductor device includes receiving an external clock signal and a control signal and generating a gated clock signal by gating an internal clock signal based on the control signal. The internal clock signal has a frequency higher than a frequency of the external clock signal. One of the external clock signal and the gated clock signal is selectively output based on the control signal.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: A particle characterization apparatus in which particles suspended in a liquid pass through an orifice or aperture for detection and characterization of the particles utilizing impedance determination. In particular, the apparatus includes a membrane of a polymer as a base material for precision machining of a sub-millimeter orifice. Forming the orifice in a polymer membrane facilitates the construction of a single use cartridge for haematology analysis due to low material and production costs.

Abstract: A word line driver for use in a semiconductor memory device includes a boosted voltage generator, a sub word line driver and a main word line driver. The boosted voltage generator generates a boosted voltage by receiving an internal power supply voltage and pumping electric charge. The sub word line driver receives the internal power supply voltage and activates a boosted voltage control signal after supplying the internal power supply voltage to a boost node in a command operating mode. The main word line driver enables a word line by supplying the boosted voltage to the boost node in response to the boosted voltage control signal in a normal operating mode, and enables the word line with the boosted voltage after boosting the word line to the internal power supply voltage by changing the boost node from the internal power supply voltage to the boosted voltage in the command operating mode.

Abstract: A Universal Serial Bus (USB) device includes an internal circuit and an interface circuit. The interface circuit is configured to interface the internal circuit and an external device for wireless USB (WUSB) communication and USB communication. The interface circuit includes a WUSB module enabling the WUSB communication, an on-the-go (OTG) module enabling the USB communication, and an interface module configured to selectively control the WUSB module and the OTG module to interface the internal circuit and the external device for the WUSB communication and the USB communication.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.