Abstract: A two-stage, Class E, fixed frequency, resonant, DC-to-DC power converter employing phase-shift control achieves outstanding performance over a full range from no load to full load. Each stage of the DC-to-DC power converter comprises a series inductor-diode network in parallel with a feed choke. Such network is connected between a power source input and a switching transistor, and it provides a fast discharge path for a resonant capacitor and lossless turn-on of the switching transistor in each power converter stage.

Abstract: A sensitivity velocity control program in a surveillance radar for distinguishing wanted moving targets from unwanted moving targets by processing radar target return data and having prestored evaluation criteria for accepting/rejecting the moving targets. The radar target return signals are processed to determine their true radial velocity and apparent radar cross section. The program evaluates these measurements based on a look-up table of preselected acceptable levels of minimum true radial velocity for each apparent radar cross section. The program declares a target acceptable when its radial velocity matches or exceeds the preselected minimum radial velocity for that radar cross section stored in a computer memory. The acceptance criteria relates to the type of target (aircraft, missile, bird, etc.) being accepted or rejected. In general, the criteria accepts large targets having low to high radial velocities.

Abstract: A spread spectrum signal detector for sampling a modulated carrier employing a zero-crossing detection means having two independent control loops, a first loop for a zero-mean threshold control and a second loop for AGC control. An IF sampler quantizeds the received spread spectrum signals at IF and provides high immunity to interference or jamming. The IF signal is sampled at a number of quarter cycle intervals to allow sampling in sequence of the in-phase (I) and quadrature-phase (Q) components. The output of the IF sampler is two bits, a sign bit and a magnitude bit. The zero-man threshold control loop using only the sign bit of the I and Q samples sets a threshold level (T0) to detect the zero-crossings of a received waveform. Two magnitude threshold levels are set at fixed offsets from the T0 threshold level.

Abstract: An apparatus and method for pseudo-random noise (PN) code correlation in a GPS receiver employing sign and magnitude input weighting for each of the in-phase (I) and quadrature-phase (Q) samples of a received PN-code modulated carrier. A programmable R factor provides input A/D sample sign and magnitude weighting control of outside crossing samples for interference rejection of other RF signals interfering with the received PN-code modulated RF carrier. The R factor weighting determines if the A/D samples are from a linear or adaptive A/D converter. In-phase reference (IREF) signals and quadrature-phase reference (QREF) signals, produced by an internally generated PN-code reference, are provided to a plurality of I and Q multi-Y-tap correlator/integrators for correlation with the I and Q samples. The apparatus correlates I and Q samples obtained from IF sampling or baseband sampling of the received PN-code modulated carrier.

Abstract: An improved means of decorrelating phase quantization errors in a phased array radar antenna using digital randomization at each of the array elements to reduce peak steering erorrs and to reduce peak sidelobe levels of the antenna. A random phase adjust term is provided to each of the array's antenna elements which comprises a distributed controller (DC) co-located with a digital phase shifter. The distributed controllers are each programmed with a random phase adjust term which represents a phase shift adjustment statistically independent from element to element. The random phase adjust term is stored in a memory located in each disbtributed controller. The distributed controller drives each element's digitally controlled phase shifter in response to a beam steering command received over a serial line. The performance improvement achieved with this decorrelation method is equivalent to that obtained by using more expensive phase shifters and adding costly randomized cables in the path to each element.

Abstract: A method and apparatus of point target filtering in a weather radar system for eliminating point targets such as airplanes in real time. A one-dimensional filter is used that operates on a single radar dwell of data at a time. The filter searches for point targets in a reflectivity data field by looking for increases and decreases in the magnitude of the radar return. Each sample volume of the radar dwell is compared to adjacent sample volumes and the differences are tested against predetermined point target thresholds. The differences greater than such predetermined thresholds are flagged. After the entire radar dwell is processed, flagged point target data in the sample volumes are replaced with the data from the sample volume just before the point target which is not considered to part of the point target. The point target filter removes the point targets and the performance limiting contamination they represent to automatic weather data processing programs.

Abstract: A surface mount device (SMD) soldering assembly having a hot bar that pivots about a point at the center of its base to accommodate non-uniform surfaces, multi-layer circuit board flatness variations and soldering-lead height differences. The hot bar is moved toward the SMD by a main mounting bracket attached to a soldering machine until it contacts the leads to be soldered. When the hot bar contacts an uneven surface, a force is applied to a set of angularly mounted slides which are coupled to ends of a rocking bracket that has the hot bar mounted to its center section. Each angular slide is attached to a support plate at an angle such that it is tangent to an arc defined by the pivot point at the center of the base of the hot bar. As the angular slides move along such arc, the hot bar pivots and thereby adjusts to any unevenness so that optimum thermal contact is made with all the leads to be soldered.

Abstract: An improved short cycled sequencer of a P-code generator is disclosed for generating a ranging code in a Global Positioning System receiver. A shift register in the sequencer has a predetermined number of stage outputs exclusive-ored with a decoded outpout of the shift register stages and the exclusive-ored output is fed back to the serial input of the shift register. At the end of sequencing through a plurality of vectors, reinitialization of the shift register occurs without having to load an initialization vector from an external source.

Abstract: A two-stage, Class E, fixed frequency, resonant, DC-to-DC power converter employing phase-shift control achieves outstanding performance over a full range from no load to full load. Each stage of the DC-to-DC power converter comprises a series inductor-diode network in parallel with a feed choke. Such network is connected between a power source input and a switching transistor, and it provides a fast discharge path for a resonant capacitor and lossless turn-on of the switching transistor in each power converter stage.

Abstract: A microprogram control unit fetches a next microinstruction based upon a branch/no-branch condition which is determined by the processing of a current microinstruction and in concurrence with the processing of the current microinstruction. Both a branch microinstruction and a next sequential microinstruction are fetched from a microinstruction memory, but only one of them, based upon the branch condition, is transferred to a microinstruction register at the start of the next microinstruction.

Abstract: A method and apparatus for real time de-aliasing of the Doppler velocity data in a weather radar system by using a Process Radials routine which processes every valid range gate along a radar dwell by determining if each range gate is within the Nyquist velocity of either the average of four preceding range gates or data from a Windfield Model. To further enhance the de-aliasing process a Process Dual Scans routine is used prior to the Process Radial routine to de-alias velocity data by comparing velocity data from two scans of different pulse repetition frequencies. Subsequent to the Process Radials routine, a Minimize Azimuthal Shear routine checks velocity discontinuities from azimuth to azimuth. The de-aliased data is transferred to an Update Windfield Model routine for quality checks of the de-aliased velocity data and updating of the Windfield Model. This complete method of de-aliasing the velocity data is performed during the real time operation of the radar system.

Abstract: A programmable volume dispensing apparatus having a positive displacement metering pump for dispensing varying amounts of high viscosity fluids such as soldering paste. The metering pump comprises a positive displacement metering pump and a digitally driven drive motor under programmable control. The drive motor is connected to the volume adjustment of the pump via a chain and sprocket mechanism. The chain and sprocket mechanism adjusts a stop which controls the stroke of the pump and the volume of fluid dispensed. In an alternate embodiment a flexible rotary drive shaft controls the stroke of the pump and the volume of fluid dispensed. Different volumes of solder can be dispensed to different areas and shapes of pads on a circuit board in accordance with preprogrammed dispensing commands.

Abstract: A flexible cable assembly having a leadless chip carrier attached to a flexible cable for providing drive signals to a matrix display element. Pins at one end of the flexible cable assembly plug into a printed wiring board and exposed metallic pads at the other end press against mating pads on the edge of the display element; the pressed together pads are held in place with a U-shaped clamp. Connection points on the leadless chip carrier are soldered to mating soldering pads on the flexible cable. A heat sink/backer is attached to the opposite side of the flexible cable under the leadless chip carrier.

Abstract: A semiconductor device referred to as complementary metal electrode semiconductor (CMES) has p-type and n-type silicon MESFETs interconnected on a substrate with an n-type barrier enhancement implanted into the p-channel of the p-type MESFET. The structure and method of fabrication are provided for forming a CMES logic inverter which has characteristics of very low power, low voltage, low noise and high speed.

Abstract: A spread spectrum signal detector for sampling a modulated carrier employing a zero-crossing detection means having two independent control loops, a first loop for a zero-mean threshold control and a second loop for AGC control. An IF sampler quantizes the received spread spectrum signals at IF and provides high immunity to interference or jamming. The IF signal is sampled at a number of quarter cycle intervals to allow sampling in sequence of the in-phase (I) and quadrature-phase (Q) components. The output of the IF sampler is two bits, a sign bit and a magnitude bit. The zero-mean threshold control loop using only the sign bit of the I and Q samples sets a threshold level (T0) to detect the zero-crossings of a received waveform. Two magnitude threshold levels are set at fixed offsets from the T0 threshold level.

Abstract: A digital system bus arbiter network which provides prioritized but equal opportunity for various devices to gain access to a common bus. The network samples the state of all pending requests for bus access, stores the current requests and generates a sequence of bus access granting signals in an order determined by the priority of the stored bus requests. When all of the bus requests have been processed for a given sample period, the network resamples currently pending bus requests and repeats the process of generating the sequence of bus granting signals on a prioritized basis. The network guarantees an equal share of bus bandwidth to each device.

Abstract: A radar system for determining not only the azimuth and range of a target but also the target height over a predetermined range of elevation angles has separate receiving and signal processing channels coupled to a dual beam antenna for processing signals returned from a single target. The output of each signal processor is coupled to a height processor which divides the sum of the received signals into the difference of the two signals. The resulting ratio is used to access a look-up table to identify the elevation angle associated with the ratio from which the height of the target is calculated. The look-up table includes correction values to compensate for the antenna pattern nonlinearity.

Abstract: A memory having an address generator in an intelligent port which generates address sequences specified by an array transformation operator in a programmable processor, thereby allowing a controlling processor to proceed immediately to the preparation of the next instruction in parallel with memory execution of a present instruction. The intelligent port of the memory creates complex data structures from input data arrays stored in memory and directs the transformation of the data structures into output data streams. The memory comprises a plurality of read-write memory banks and a bank of read-only memory interconnected through intelligent ports and busses to other units of the processor. An arbitration and switching network assigns memory banks to the intelligent ports.

Abstract: A counterbalance mechanism for negating the force of gravity when moving a display cabinet shelf up or down. The mechanism has a torsion spring counterbalance on a shaft extending the width of the shelf and gears at each end of the shaft which engage travelling rack gears attached beneath each end of the shelf. The shelf includes integral guide rails rolling on four bearings attached to the stationary frame of the cabinet. The use of spiral gears compensates for the spring torque variation and provides constant tangential gear force on the shelf regardless of the vertical position of the shelf. Having gears at each side of the moving shelf joined by a common shaft minimizes side-to-side tilting.

Abstract: A semiconductor device referred to as complementary metal electrode semiconductor (CMES) has p-type and n-type silicon MESFETs interconnected on a substrate with an n-type barrier enhancement implanted into the p-channel of the p-type MESFET. The structure and method of fabrication are provided for forming a CMES logic inverter which has characteristics of very low power, low voltage, low noise and high speed.