Abstract: A cartesian to polar coordinate converter using a cordic magnitude circuit for estimating the magnitude and angle of a vector from its known orthogonal components. The vector is described in cartesian coordinates by the complex number I+jQ. The magnitude of the vector and its angle are approximated by an iterative process of successively rotating the vector toward one of the orthogonal axes and the cordic magnitude circuit is implemented in one very large scale integrated (VLSI) complementary metal-oxide semiconductor (CMOS) chip. In systems using a typical cordic magnitude circuit, accuracy increases in direct proportion to the number of rotations. The increase is accompanied by a need for an increased word size which results in a slower operating speed. The improved cordic magnitude circuit achieves higher precision without the need for a larger word size.

Abstract: A moving target detector (MTD) in a radar system uses corrected weighting coefficients to compensate for pulse stagger effect on transmitted pulses. Transmitted pulses are sampled when the radar is switched to a test mode for determining a correction factor which is used to calculate the corrected weighting coefficients. The radar return signals are processed in the MTD by a finite impulse response (FIR) filter using the stored corrected weighting coefficients calculated for each sequence of transmitted pulses including block stagger and pulse stagger sequences.

Abstract: A very high density, multiple contact connector has low-inductance power and ground planes and gold dot contacts for providing a controlled impedance environment to a module assembly by minimizing undesirable effects such as ground-noise and reflections while assuring operation at interconnect bandwidths up to 6 GHz. The controlled impedance connector connects two printed wiring boards (PWBs) comprising surface mounted devices to a motherboard. The PWBs are bonded to opposite sides of a central heat frame. The connector has two flexible circuits containing a total of 460 gold dot signal connections plus a plurality of separate gold dot power and ground connections. Signal runs between the PWBs and the connector flexible circuits are interconnected using copper fingers soldered to pads on the PWBs. Power and ground planes connect to the PWBs via gold dot contacts on the inside of the flexible circuit surface to pads on the PWBs. The connector is a true zero insertion force design.

Abstract: A pipeline computer architecture having two interconnected microengines operating simultaneously in an instruction preparation unit of a pipeline computer system. Each microengine operates on the same portion or different portions of an instruction concurrently within the same clock cycle. To assure coordination, one microengine is declared the executive or attribute generator and the other the main microengine. The main microengine generates routines to control the instruction preparation unit hardware. The executive microengine prepares the next tank in parallel and supplies arguments to the main microengine as the main microengine generates its current routine. At the completion of a routine performed by the main microengine, it signals the executive microengine to obtain the next task and associated parameters.

Abstract: Fault insertion circuits under programmable control and resident in an integrated circuit (LSI or VLSI) insert transient and intermittent fault classes in addition to a permanent fault class into functional logic on such integrated circuit. Specific fault types programmable for each fault class include a stuck-open fault and bridging faults both wired-AND and wired-OR. The programmable fault insertion circuitry on each integrated circuit interfaces directly or indirectly with a BIT maintenance controller. In addition to verifying test software, a fault tolerant system's error detection and recovery circuits may be verified by fault insertion testing using the transient and intermittent fault insertions.

Abstract: A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mode select signal. Each stage of the 4-bit counting section comprises a propagate/kill/generate gate for determining the status of a carry signal to a next stage, except the last stage of a 4-bit section, which does not require such a gate because it is coupled to a carry-forward generator along with the outputs from the other preceeding stages in the section. Each 4-bit section performs the counting function through a successive process of modulo-two sums of a lower order carry and the current state of a counter stage without the need for cumbersome gating structures.

Abstract: A variable field content addressable memory (VFCAM) unit cell comprises a 4-bit content addressable memory, a programmer and a field selector. A limited capability of comparing between limits is provided by using mask bits at the data line inputs to the VFCAM unit cell. A plurality of VFCAM unit cells may be cascaded vertically and horizontally to provide a Y words by X bits VFCAM array. The VFCAM array is programmable by a field code coupled to field partition logic which selects the same number of fields in all memory locations and the number of bits in each field, and an operational VFCAM system results when the VFCAM array is coupled to an input address decoder, an I/O register and an output encoder.

Abstract: An acceleration-sensitive safety brake having two semi-cylindrical flyweights in a single plane, connected near the geometric center of their semi-circular cross-section to eccentric pivot pins protruding from a rotating hub for limiting the acceleration of an apparatus. The flyweights are held in a centered position during normal operation by the force of a helical spring acting on split halves of semicylindrical cavities in each of the adjacent faces of the flyweights. The flyweights are located in cylindrical hole of a fixed housing which is concentric with the rotating hub. Rapid angular acceleration of the hub applies both a rotational and translational motion to the flyweights. Whenever the pivot pins apply a force to the flyweights which is greater than the force exerted by the centering spring, the flyweights move in opposite directions, relative to each other, and push against the fixed housing creating a braking action.

Abstract: A microprogrammed control unit of an information processing system having a control sequencer with dual microprogram counters for performing microdiagnostics simultaneously with performing macroprograms. The microdiagnostics comprise background and operability tests, the background tests being interleaved with macroinstruction operations under the control of the two independent microprogam counters. The background tests are run during processor idle time and the operability tests are executed at processor turn-on. The organization of the microdiagnostics into a hierarchical structure allows the use of the same microprogrammed test module for both the background and operability microdiagnostic tests. A prediction/residual coding technique provides fault detection for address and data information within the control sequencer.

Abstract: A memory having an address generator which generates nested address sequences specified by an array transformation operator in a programmable processor, thereby allowing a controlling processor to proceed immediately to the preparation of the next instruction in parallel with memory execution of a complex present instruction. The address generator generates row and column indices specified by the array transformation operator comprising an initial reference point parameter, a boundary parameter and a plurality of displacement and length parameters expressed relative to the initial reference point. Address sequences for data representing a vector, matrix, or block are generated in a single memory in accordance with the factored series of nested addressing sequences specified by the array transformation.

Abstract: A computer controlled laser apparatus having multiple mirrors positioned along the locus of an ellipse having a first focus point at the center of an angle select mirror and a second focus point on a workpiece to be soldered. Such a geometrical configuration permits a computer to efficiently control the reflection of the laser beam onto the workpiece at different angles of incidence while maintaining a constant laser beam pathlength without requiring refocusing of the beam as it is moved from angle to angle.

Abstract: A CMOS output driver having precise control of rise and fall times of signals generated from the output driver on a VLSI semiconductor chip. Two time-dependent voltage generators provide a separate ramp signal to each one of the gates of a CMOS inverter circuit. The ramp signal characteristics of each voltage generator are determined by the combination of a controlled current source charging a known capacitance.

Abstract: A 1.2 .mu.m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens in the next stage. Each 4-bit section performs the counting function through a successive process of additions of a lowest order carry-bit input. A count enable signal serves to enable the count process as well as serving as a carry-bit input to a first stage. Count enable effects a counter reset when in a logic "zero" state. Once the count enable is raised to the logic "one" state, the process of counting begins with the rising edge of the first clock pulse. As long as the count enable is maintained, counting continues. When the count enable is reduced to a "zero" state, counting is terminated, with a counter reset occurring on the next sequential rising edge of the clock.

Abstract: A floating point computation unit having an arithmetic unit employing two guard digits for preserving information needed for rounding and an indicator generator for providing an indicator signal to a precision rounding apparatus. The indicator generator detects any digits beyond the guard digits of a shifted operand instead of waiting to detect such digits in the mantissa produced by an add or subtract cycle. The indicator generator comprises a priority encoder network coupled to a comparator for determining whether or not the least significant digits beyond the guard digits of the shifted mantissa are all zeros.

Abstract: Vector magnitude approximating logic using logarithms of the vector's orthogonal components to select multiplier scaling constants and to minimize arithmetic-function and hardware complexity. The apparatus is particularly applicable to a high-throughput, pipelined, digital signal processing application such as radar. The vector magnitude is approximated by multiplying each component of a complex number representing the vector by selected scaling constants and then by summing the two resulting products. The scaling constants are selected by feeding each orthogonal component of the vector into one of two identical logic arrays which determine the base-2 logarithm of the absolute value of each component.

Abstract: A digital system comprising a synchronous fastbus for interconnecting a cluster of devices such as processors and for interconnecting a plurality of said clusters. Information is transferred over the synchronous fastbus using a parallel digital word information packet. All required bus control signals including acknowledge and non-acknowledge signals take place within the same packet transfer fastbus cycle time. A command information packet is transferred over the fastbus separately from a response information packet thereby leaving the fastbus free until a response packet is returned to the requestor. During the interim other devices are allowed to access the fastbus, thereby increasing significantly fastbus utilization.

Abstract: A radar receiver having a feed-forward control circuit for adjusting the automatic gain control (AGC) setting in 6 dB increments for each range cell in a next sweep based on the AGC setting of each corresponding range cell in the present sweep, the magnitude of the larger of the in-phase (I) or quadrature (Q) components of the video signals of the present sweep from an A/D converter, the status of present sweep and previous sweep A/D limit conditions, and a selected guardband thereby holding the level of the radar return signal within the dynamic range of the A/D converter. The AGC setting is adjusted using a switchable attenuator which changes the level of the video signal into the A/D converter in 6 dB increments, each increment corresponding to a common I and Q data exponent directly used for floating point signal processing.

Abstract: Unified CMOS logic circuits are based on a structured implementation of transmission-gates. The basic logic building blocks for AND and OR circuits comprise a plurality of transmission-gates some of which may be simplified to a reduced form of a single pass transistor resulting in fewer transistors for implementing logic functions without loss of logic circuit performance characteristics. Three variable logic functions and higher order logic functions are easily implemented. Generally, the required VLSI chip area is minimized as a result of this structured transmission-gate approach.

Abstract: A vernier address scale reduces the number of addressable memory locations required for numerical look-up tables. Read-only memories (ROMs) store the data of linear or non-linear functions. Decoders determine which ROM is selected and advantage is taken of accuracy improvement as numbers become larger by dropping least significant bits as the vernier address scale moves from one ROM table to another. Accuracy is further improved by using a method of one-half level quantization step for rounding. This reduces the size of numerical tables for math processing of reciprocals, roots of numbers, powers of numbers, logarithms, trigonometric and exponential functions.

Abstract: A radar receiver having a feed-forward control circuit for adjusting the automatic gain control (AGC) setting in 6 dB increments for each range cell in a next sweep based on the AGC setting of each corresponding range cell in the present sweep, the magnitude of the larger of the in-phase (I) or quadrature (Q) components of the video signals of the present sweep from an A/D converter, the status of present sweep and previous sweep A/D limit conditions, and a selected guardband thereby holding the level of the radar return signal within the dynamic range of the A/D converter. The AGC setting is adjusted using a switchable attenuator which changes the level of the video signal into the A/D converter in 6 dB increments, each increment corresponding to a common I and Q data exponent directly used for floating point signal processing.