Abstract: A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias.

Abstract: Apparatus and methods for verification of the dimensions of a semiconductor manufacturing peripheral are disclosed, in which the peripheral, e.g., a wafer cassette, is positioned between, and is enveloped by, an emitter housing and an opposing receiver housing adapted for emitting and receiving, respectively, light from a selected portion of the electromagnetic spectrum, preferably infrared. The measured light is used to verify the dimensions of the target peripheral in comparison with a pre-selected standard.

Abstract: Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the collet using a vacuum force. A pushing force is also exerted on the die adjacent to the applied vacuum force. The pushing force opposes flexion of the die in the direction of the vacuum force. In further steps, the die is placed on a die pad, and die attach adhesive is interposed between the die and the die pad. A preferred method includes applying a pushing force to bow the central region of the die toward the die pad. In a preferred apparatus of the invention, a collet has a body including a bearing surface for receiving a die and a vacuum for holding it. A chamber encompassed by the bearing surface is adapted for applying the force of expelled gas against a die borne on the bearing surface.

Abstract: A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad.

Abstract: Attaching a semiconductor chip to a substrate by applying mechanical vibrations (150) to a polymeric compound (130) and the contacting areas (114, 124) of a first (113) and a second (121) metallic member immersed in the compound, while the two metallic members approach (140) each other until they touch. The mechanical vibration causes displacements of the first member relative to the second member, and the vibration includes displacements (150) oriented at right angles to the direction (140) of the approach. The polymeric compound (130) includes a non-conductive adhesive resin paste (NCP) and filler particles; the paste is deposited before the attaching step. The first member (113) is affixed to the chip and the second member (121) to the substrate.

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (402) and a plurality of lead segments (403). Covering the base metal are, consecutively, a nickel layer (301) on the base metal, and a continuous layer of noble metal, which consists of a gold layer (201) on the nickel layer, and an outermost palladium layer (202) on the gold layer. A semiconductor chip (410) is attached to the chip mount pad and conductive connections (412) span from the chip to the lead segments. Polymeric encapsulation compound (420) covers the chip, the connections, and portions of the lead segments. In QFN devices with straight sides (501), the compound forms a surface (421) coplanar with the outermost palladium layer (202) on the un-encapsulated leadframe surfaces.

Abstract: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.

Abstract: The present invention implements a mechanism using an inter-connection layer to couple a plurality of integrated circuit devices to a printed circuit board, thereby eliminating the need for sockets to hold the integrated circuit devices on the printed circuit board. The mechanism of the present invention is operative for integrated circuit devices packaged in a ball grid array, a quad flat pack or a leadless quad flat pack. The present invention also provides a mechanism to efficiently transfer a plurality of integrated circuit devices from an integrated circuit device delivery tray to a burn-in board in a single process without requiring an autoloader, resulting in increased transfer reliability and both cost and space savings.

Abstract: A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere (105) is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate (110) with a chip attachment location and a third set of contact pads (112) near the location. Low profile bond wires (130) span between the pads of the third set and the second set. A second semiconductor chip (140) of a size has a fourth set of contact pads (141) at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set.

Abstract: Methods and devices are disclosed for cleaning contactors equipped with contact pins such as pogo pins include steps which may be performed in concert with common semiconductor device testing processes using automatic test equipment and associated handlers. The preferred embodiments of the invention include method steps for mounting a surrogate cleaning device in a tester load board socket and applying the contact pins associated with automatic test equipment to the surrogate cleaning device for cleaning.

Abstract: A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second surfaces (111b) are coplanar (130) with the passive chip surface (101b). Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound (150) covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar (130) with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 ?m. Reflow metals may be on the passive chip surface and the second segment surfaces.

Abstract: A method for treating an area of a semiconductor wafer surface with a laser for reducing stress concentrations is disclosed. The wafer treatment method discloses treating an area of a wafer surface with a laser beam, wherein the treated area is ablated or melted by the beam and re-solidifies into a more planar profile, thereby reducing areas of stress concentration and stress risers that contribute to cracking and chipping during wafer singulation. Preferably, the treated area has a width less than that of a scribe street, but wider than the kerf created by a wafer dicing blade. Consequently, when the wafer is singulated, the dicing blade will preferably saw through treated areas only. It will be understood that the method of the preferred embodiments may be used to treat other areas of stress concentration and surface discontinuities on the wafer, as desired.

Abstract: A packaged integrated circuit (IC) (100) includes a first substrate (110) including a first plurality of layers and first circuit coupling features (112) at an upper surface of the first substrate (110). The first plurality of layers include a first electromagnetic interference shielding layer (132). The packaged IC also includes a second substrate (106) having an upper surface attached to a lower surface of the first substrate (110) by an electrically conductive adhesive material (136). The second substrate (106) includes a second plurality of layers and a second circuit coupling feature (108) at a lower surface of the second substrate (106). The first plurality of layers includes a second EMI shielding layer (134). The packaged IC further includes a functional die (124) disposed between the first (110) and the second (106) substrates and functionally coupled to the first (112) and/or the second (108) circuit coupling features.

Abstract: A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting plate.

Abstract: An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a ferromagnetic body (111) and a wire (104) wrapped around the body to form at least a portion of a loop; the wire ends (104a) are connected to the chips. The assembly is attached to a substrate (103), which may be a leadframe. The device may be encapsulated in molding compound (140) so that the inductor can double as a heat spreader (111c), enhancing the thermal device characteristics.

Abstract: Systems and methods are provided for contactless testing of a wafer containing at least one integrated circuit. A test component responds to a supply voltage to indicate at least one property of the wafer. A voltage source wirelessly receives power from an external source and produces the supply voltage. A reference generator generates a reference voltage, having a known magnitude, from the supply voltage. A voltage evaluation component modifies the response of the test component as to represent a magnitude of the supply voltage.

Abstract: The present invention relates to an integrated electronic device for digital signal processing, which includes a reference clock input for receiving a reference clock, a phase locked loop (PLL), a phase interpolator (PI) coupled to the phase locked loop (PLL) for shifting a phase of an output clock signal of the PLL in a stepwise manner so as to generate a shifted output clock signal (PHI_out), a logic stage for determining the state of the reference clock signal (REF_CLK) multiple times during an edge of the shifted output clock for each phase shift, a storing means for storing information whether or not the determined state of the reference clock signal (REF_CLK) is stable for a phase of the shifted output clock signal (PHI_out), and an interface configured to read out the stored information for determining the jitter of the shifted output clock signal (PHI_OUT).

Abstract: A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part (1701) with a plurality of terminal pads (1702). This part is spaced from the workpiece, and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element (1203) interconnects each of the contact pads with its respective terminal pad. Thermoplastic material (1204) fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline (1711) substantially in line with the outline of the workpiece, and fills the space (1707) substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.

Abstract: The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe arrays and package arrays used for the manufacture of IC packages by transfer molding processes include a locking feature adapted for encapsulation. The locking feature is situated in a strap of the leadframe array overlying a gate between mold cavities. The strap lock formed by curing encapsulant in the locking feature of the strap strengthens the resulting package array and provides improved mold extraction and handling characteristics.

Abstract: Methods and systems are disclosed for forming secure wirebonds between electrical contacts in electronic device assemblies. Representative embodiments of the invention are described for forming a wirebond including system components and method steps for generating electromagnetic energy from a heat source and transmitting heat to a ball formed on a bondwire. Subsequently, pressure applied to the ball at the bonding site is used in the formation of a wirebond.