Abstract: An electron-beam size measuring apparatus includes: electron beam irradiating means that irradiates an electron beam on a surface of a sample; detection means that detects electrons emitted from the sample; distance measurement means that measures the distance between the sample and a secondary electron control electrode of the detection means; a stage on which the sample is mounted; and control means which adjusts the height of the stage so that the distance measured by the distance measurement means would be equal to a predetermined fixed distance, which applies a control voltage to the secondary electron control electrode of the detection means, the control voltage predetermined so as to allow the sample surface potential to become constant with the sample positioned at the fixed distance, and which causes the electron beam to be irradiated by applying a predetermined accelerating voltage.

Abstract: A consumption current balance circuit reduces the layout area and suppresses the deterioration of accuracy of a delay time caused by a temperature variation due to a power variation of a delay circuit itself or caused by a load variation of a power supply. The consumption current balance circuit includes a delay circuit for giving a delay time to a timing pulse signal, a compensation circuit for interpolating the consumption current of the delay circuit, a ring oscillator provided in the same power supply area as the delay circuit; an output period counter for measuring the output period of the ring oscillator; and a heater circuit current amount adjusting circuit for adjusting the current amount of the heater circuit to minimize the difference in the output period between the stand-by state and the active state of the ring oscillator.

Abstract: A gain of a buffer provided on a performance board of a semiconductor test apparatus can be adjusted for testing image sensors with high accuracy. The performance board includes buffers for driving cables, and switches for inputting either a measurement signal from a device under measurement or a reference signal output from a reference signal generator. During calibration, the switches are turned to terminals to which the reference signal is input, such that the reference signal is applied to the buffers. Then, the gains of the buffers are corrected so that the output of an analog capture board has a desired value.

Abstract: A PLL and DLL are designed such that the power consumption can be reduced, the size can be easily reduced, the band of the locked loop can be a higher one, and the reliability can be improved. There are provided a phase comparator for measuring a feedback signal in synchronism with an input signal and outputting a phase signal representing the lead or lag of the phase of the feedback signal, a counter for increasing the number of bits representing “H” in a control signal when the phase signal represents the lead or decreasing the number of bits representing “H” in the control signal when the phase signal represents the lag, and a ring oscillator for increasing the oscillation period when the number of bits representing “H” increases or decreasing the oscillation period when the number of bits representing “H” decreases.

Abstract: A connection unit for electrically connecting a DUT mounting board, on which an IC socket is mounted, with a testing apparatus for testing an electronic device inserted into the IC socket, the connection unit has a holding substrate provided to face the DUT mounting board and a connection-unit-side connector, which is provided on the holding substrate to be able to change a position of the connection-unit-side connector on the holding substrate, for being connected to a performance-board-side connector included in the DUT mounting board.

Abstract: A characteristic test of a DUT having a low transmission line driving capability can be performed with a simple configuration and low cost. An impedance matching circuit is connected between a transmission line and a DUT in an input-output circuit of a semiconductor test apparatus. The impedance matching circuit includes: a resistance; an analog computing unit which multiplies a voltage from one end of the resistance by a predetermined number, subtracts a voltage from the other end of the resistance from the voltage multiplied by the predetermined number and outputs a resultant voltage; and a buffer which outputs a signal from the analog computing unit with low impedance. The impedance matching circuit produces an output signal from the DUT with low impedance, thereby sufficiently driving the transmission line.

Abstract: A PLL and DLL are designed such that the power consumption is reduced, the size is reduced, the band width of the locked loop is increased, and the reliability is improved. There are provided a phase comparator for measuring the value of a feedback signal in synchronism with an input signal and outputting a phase signal representing the lead or lag of the phase of the feedback signal, a counter for increasing by one the number of bits representing “H” in a control signal when the phase signal represents the lead of the phase or decreasing by one the number of bits representing “H” in the control signal when the phase signal represents the lag of the phase, and a ring oscillator for increasing the oscillation period when the number of bits representing “H” in the control signal increases or decreasing the oscillation period when the number of bits representing “H” decreases.

Abstract: A system for mating and demating a plurality of connectors mounted on a socket board with and from a plurality of corresponding connectors mounted on a motherboard includes: an adapter that is arranged above a surface opposite to the socket board surface on which the connectors are arranged and is movable in a direction in which the connectors are mated and demated; pressing means which contacts the surface of the socket board on which the semiconductor components are placed to press the socket board to the motherboard by lowering the adapter; and pulling means each of which engages with an engaging hole formed in the socket board and pulls the socket board in the direction in which the socket board is separated from the motherboard by lifting the adapter.

Abstract: A multicolumn electron-beam exposure system includes: a plurality of column cells, which are arranged above a wafer, and each of which includes an electron gun and deflection means which deflects an electron beam irradiated from the electron gun; common storage means which stores common exposure data used by the plurality of column cells; and size data correcting means which is provided to each of the column cells, and which receives size data on a variable-shaped beam from the common storage means, thus outputting an amount of correction to the size data. The amount of correction is the size data on the variable-shaped beam, which corresponds to the difference between the size of a resist pattern, which has been formed by specifying an intended pattern size and a reference light exposure, and the intended pattern size.

Abstract: In a tentative target value calculation section 28, a predetermined value is subtracted from (or added to) a target value Exp to calculate a tentative target value ExpB. In a binary search executing section 25, binary search is executed, and a searching region is limited to a certain region including this tentative target value ExpB. Next, in a sequential search executing section 29, the target value Exp is searched for in an increasing direction from the tentative target value ExpB which is a start point in the limited searching region. Accordingly, both drop prevention of measurement precision and reduction of searching time are achieved consistently, and a target value is securely and normally found in a case where a sequence constituting a searching object indicates an ascending-order sequence including a decrease in a part.

Abstract: An electron beam generator for multiple columns includes: a plurality of cathodes, to which a single acceleration voltage supply applies a negative acceleration voltage, and which thus generates thermoelectrons; a grid for each of the plurality of cathodes, the grid converging the thermoelectrons emitted to form a beam of electrons; a grid voltage supply for giving the grid a potential which is negative relative to a potential of the cathode; and a control circuit for each cathode, for controlling the potential of the grid. The control circuit includes a current direction restricting element connected between a positive electrode of the grid voltage supply and the cathode, and a grid current supplied from the grid voltage supply is caused to flow to the cathode through the current direction restricting element.

Abstract: A mask inspection apparatus includes: an electron gun for generating an electron beam; an exposure mask for shaping the electron beam into a predetermined cross-sectional shape; means for scanning the electron beam shaped by the exposure mask; means for selecting and transmitting part of the shaped electron beam, which selecting means includes a thin film having a small transmission aperture transmitting the electron beam scanned by the scanning means and includes a thick substrate having an opening larger than the small transmission aperture and a thickness greater than that of the thin film; and means for detecting the electron beam passed through the selecting means and outputting a current signal. The detecting means includes: a reflective body for reflecting the electron beam selected by the selecting means; and a detector for detecting the electron beam reflected by the reflective body.

Abstract: A probe card on which micro probe needles are arranged at high density and with high precision without need of a complicated structure or variation in needle height. A probe card 1 installed in a wafer tester includes a board 2 having a wiring pattern for transmitting a test signal to be impressed on a wafer under test, a built-up board 10 formed on the surface of the board 2, a comb-shaped silicon-made probe needle 20 arranged on the built-up board 10 and connected to the surface wiring pattern 11, and a flat portion 12 formed by plating on the surface wiring pattern 11 on the built-up board 10 and having a surface flattened by polishing. The probe needle 20 is loaded on the flat portion 12 and thus mounted on the board 2.

Abstract: The electrostatic chuck 101 where pairs of electrodes 3a/3b, 4a/4b and 5a/5b to which voltages are applied are embedded in the main body 1, and where a substrate 110 is placed and held on the surface of the main body 1, includes a first electrode group constituted of one pair or more of electrodes 3a/3b arranged in a center region 41 inside the main body 1, and a second electrode group constituted of one pair or more of electrodes 4a/4b and 5a/5b arranged in outer peripheral portions 42 and 43 surrounding the center region 41.

Abstract: A YIG device comprises a resonator including a YIG element 16 of a single crystalline yttrium iron garnet having a part of yttrium substituted with gadolinium, which is formed in a spherical shape, and magnetic field applying means 20 for applying a magnetic field to the YIG element 16 to resonate the YIG element, whereby the YIG device can have a small ?H and a large threshold electric power for generating the resonance saturation.

Abstract: An electron-beam exposure system includes: density-per-area map generating means configured to divide a certain area on which an electron beam is irradiated into meshes, to figure out a ratio of an area of patterns to be irradiated on each divided region to an area of the divided region, thus to generate a density-per-area map; and proximity-effect correcting means configured to correct exposure of the electron beam by referring to the density-per-area map.

Abstract: Good device PASS/FAIL determination is realized by measuring timings of a cross point of differential clock signals CLK and a data signal DATA output from a DUT, and obtaining a relative phase difference between both signals. A semiconductor test apparatus comprises differential signal timing measurement means for outputting cross point information Tcross obtained by a timing of a cross point of one of differential signals, non-differential signal timing measurement means for outputting data change point information Tdata obtained by a timing of transition of a logic of the other non-differential signal output, phase difference calculation means for outputting a phase difference ?T between the cross point information Tcross and the data change point information Tdata, and PASS/FAIL determination means for determining PASS/FAIL of a relative positional relationship of the DUT based on a predetermined threshold value.

Abstract: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator 20 which obtains clocks input from a DUT 1 by a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolator 20 which obtains output data input from the DUT 1 by a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selector 30 which switches the time-sequential level data obtained by the time interpolators 20 and selectively outputs level data indicating rising and/or falling edges of the level data.

Abstract: A characteristic test of a DUT having a low transmission line driving capability can be performed with a simple configuration and low cost. An impedance matching circuit is connected between a transmission line and a DUT in an input-output circuit of a semiconductor test apparatus. The impedance matching circuit includes: a resistance; an analog computing unit which multiplies a voltage from one end of the resistance by a predetermined number, subtracts a voltage from the other end of the resistance from the voltage multiplied by the predetermined number and outputs a resultant voltage; and a buffer which outputs a signal from the analog computing unit with low impedance. The impedance matching circuit produces an output signal from the DUT with low impedance, thereby sufficiently driving the transmission line.

Abstract: A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM) 10 containing predetermined timing data; a plurality of down counters 20 for loading the timing data from the TMM and outputting a pulse signal at the timing indicated by the timing data; an address selection circuit 40 for specifying one or two TMM addresses by switching and outputting corresponding one or plural timing data; a load data switching circuit 50 for loading the plural timing data to the plural down counters cascaded and outputting one timing pulse signal; and a timing data selection circuit 60 for selecting one of the pulse signals. The plural timing data are generated by dividing the timing memory into a plurality of memory regions either in a column or row direction.