Patents Assigned to Advantest Corp.
  • Packaging and interconnection of contact structure
    Patent number: 7276920
    Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component. The packaging and interconnection includes a contact structure made of conductive material and formed on a contact substrate, a contact trace formed on the contact substrate and connected to the contact structure, a contact pad formed on a bottom surface of the contact substrate and connected to the contact structure through a via hole and the contact trace, a contact target provided at an outer periphery of the contact structure to be electrically connected with the contact pad, and a conductive member for connecting the contact pad and the contact target.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: October 2, 2007
    Assignee: Advantest Corp.
    Inventors: Mark R. Jones, Theodore A. Khoury
  • Method and system for detecting chemical substance
    Patent number: 7265369
    Abstract: A chemical detecting apparatus includes a substrate 10 for chemicals in gas-to-be-monitored to be adsorbed to, a substrate adsorption rate improving means 12 which enhances the adsorption of the chemical in the gas-to-be-monitored to the substrate, an infrared light source 20 which applies an infrared light to the substrate 10 with the chemical adsorbed to, and an infrared light detector 22 which detects the infrared light which has made multiple reflections in the substrate 10 and exited the substrate. Thus, chemicals present in environments can be detected at high speed and with high sensitivity.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: September 4, 2007
    Assignee: Advantest Corp.
    Inventor: Kazuyuki Maruo
  • Probability estimating apparatus and method for peak-to-peak clock skews
    Patent number: 7263150
    Abstract: A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for estimating the generation probability of the peak-to-peak value or peak value of the clock skews. The probability estimating apparatus for peak-to-peak values in clock skews includes a clock skew estimator for estimating clock skew sequences among the plurality of clock signals under test and a probability estimator for determining a generation probability of the peak-to-peak values in the clock skews among the plurality of clock signals under test based on the clock skew sequences from the clock skew estimator by applying Rayleigh distribution. The generation probability of the peak-to-peak value is estimated based on RMS values of the clock signals and the Rayleigh distribution.
    Type: Grant
    Filed: February 23, 2002
    Date of Patent: August 28, 2007
    Assignee: Advantest Corp.
    Inventors: Masahiro Ishida, Takahiro Yamaguchi, Mani Soma
  • Semiconductor memory test apparatus and method for address generation for defect analysis
    Patent number: 7240256
    Abstract: There is disclosed a semiconductor memory test apparatus capable of easily generating an address to be input into a failure analysis memory for testing a memory device having a burst function which automatically generates addresses for banks therein. Each of registers corresponding to the banks of the memory device holds a line address of the corresponding bank. When a start address of one of the banks is input to the memory device, a line address of the same bank as the start address is read out from the register corresponding to the bank and output to a failure analysis memory together with the start address. Furthermore, during burst operation of the bank, the registers output the line address to the failure analysis memory together the same line address as the memory device generated by calculating the start address for each clock cycle.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: July 3, 2007
    Assignee: Advantest Corp.
    Inventor: Tomoyuki Yamane
  • Timing generator and semiconductor testing device
    Patent number: 7240269
    Abstract: A timing generator f or a semiconductor test device reduces pattern-dependent jitters and timing errors of timing pulse signals. In the timing generator, a delaying circuit (variable delaying means, clock signal delaying circuit) is disposed on an input terminal side of a clock signal of a signal input/output circuit having the flip-flop (reference signal delaying means) which outputs an output signal in accordance with an input timing of the delayed clock signal. The clock signal is delayed by the delaying circuit. The clock signal delaying circuit may be replaced with a phase locked loop circuit.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: July 3, 2007
    Assignee: Advantest Corp.
    Inventor: Takashi Ochi
  • Format control circuit and semiconductor test device
    Patent number: 7216281
    Abstract: There is provided a semiconductor test apparatus which assuredly detects an inhibited edge only which affects a test pattern and truly requires an error warning. This semiconductor test apparatus includes: a real time selector which receives a plurality of sets of waveform data, receives a plurality of sets of timing data, selects and outputs predetermined waveform data and timing data, inhibits a next edge immediately following the current edge and outputs an inhibiting signal when an edge with the same polarity which is continuous in an interval shorter than a proximity limit time exists in the waveform data; and a detector which receives the waveform data, the timing data and the open signal, and outputs fail signal when an edge with a polarity reverse to that of an inhibited edge exists in the proximity limit time before the inhibited edge.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 8, 2007
    Assignee: Advantest Corp.
    Inventor: Katsumi Ochiai
  • Semiconductor test instrument
    Patent number: 7196534
    Abstract: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator 20 which obtains clocks input from a DUT 1 by a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolator 20 which obtains output data input from the DUT 1 by a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selector 30 which switches the time-sequential level data obtained by the time interpolators 20 and selectively outputs level data indicating rising and/or falling edges of the level data.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: March 27, 2007
    Assignee: Advantest Corp.
    Inventor: Hideyuki Oshima
  • Event based test method for debugging timing related failures in integrated circuits
    Patent number: 7194668
    Abstract: A test method for debugging failures of an IC device with use of an event based semiconductor test system is capable of distinguishing a timing related failure from other failures. The test method includes the steps of: applying a test signal to a DUT and evaluating a response output of the DUT, detecting a failure in the response output, identifying a reference clock signal related to the failure, identifying a portion of the reference clock signal that is directly related to the failure, and incrementally changing a timing of events for the identified portion of the reference clock signal to detect change in the response output from the DUT.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: March 20, 2007
    Assignee: Advantest Corp.
    Inventors: Ankan Pramanick, Siddharth Sawe, Rochit Rajsuman
  • Radiowave monitoring method and apparatus
    Patent number: 7187324
    Abstract: Arrival directions and patterns of intensities of radiowaves are observed by a monitor station 12a. An observed pattern given by the monitor station 12a is compared with simulated patterns of intensities and emitting directions of a simulated radiowave, and a position whose simulated pattern shows the best correlation with the observed pattern given by the monitor station 12a is identified as a location of the radiowave emitting source. Accordingly, a time for preparing data base by the radiowave propagation simulation can be decreased, and the radiowave monitor can be more efficient.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: March 6, 2007
    Assignee: Advantest Corp.
    Inventor: Hitoshi Kitayoshi
  • Semiconductor test device having clock recovery circuit
    Patent number: 7187192
    Abstract: A semiconductor test device for acquiring a multiplexed clock signal from LSI output data and using the clock to test the LSI. The device includes a time interpolator and registers connected in series. The time interpolator has flip-flops connected in parallel for receiving output data from an LSI under test, a delay circuit for successively inputting strobes delayed at a constant timing interval to the flip-flops and outputting time-series level data, and an encoder for receiving the time-series level data from the flip-flops and encoding it into position data indicating an edge timing. The registers successively store position data from the encoder and output them at a predetermined timing. The device further includes a digital filter for outputting the position data from the registers as a recovery clock.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: March 6, 2007
    Assignee: Advantest Corp.
    Inventors: Hideyuki Oshima, Yasutaka Tsuruki
  • Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing
    Patent number: 7178115
    Abstract: A manufacturing process for LSIs uses an event tester simulator and an event tester to avoid prototype hold. In the LSI manufacturing method an LSI is designed under an EDA (electronic design automation) environment to produce design data of a designed LSI, and logic simulation is performed on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of an event format as a result of the logic simulation. Then, simulation data files are verified with use of the design data and the testbench by operating an event tester simulator, and a prototype LSI is produced through a fabrication provider by using the design data. The prototype LSI is tested by an event tester by using the test vector file and the simulation data files and test results is feedbacked to the EDA environment or the fabrication provider.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: February 13, 2007
    Assignee: Advantest Corp.
    Inventors: Rochit Rajsuman, Hiroaki Yamoto
  • Semiconductor test system
    Patent number: 7173443
    Abstract: A mixed signal test system for testing a semiconductor device having both an analog function and a digital function achieves improved resolution and low cost. The test system is formed of a functional test unit for testing a digital function of a device under test (DUT), an analog test unit (ATU) for testing an analog function of the DUT, and a synchronous control unit for synchronizing operations between the functional test unit and the analog test unit. The analog test unit includes a digitizer for converting an analog output of the DUT into a digital signal, and an acquisition memory for storing the digital signal from the digitizer in specified addresses. The wave form of the analog output is repeated by a plurality of cycles and a sampling clock for the digitizer is phase shifted by a predetermined amount for each cycle.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: February 6, 2007
    Assignee: Advantest Corp.
    Inventor: Koji Asami
  • Event processing apparatus and method for high speed event based test system
    Patent number: 7171602
    Abstract: An apparatus and method for computing event timing for high speed event based test system. The event processing apparatus includes an event memory for storing event data of each event where the event data includes timing data for each event which is formed with an integer multiple of a clock period and a fraction of the clock period, an event summing logic for accumulating the timing data and producing the accumulated timing data in a parallel form, and an event generator for generating events specified by the event data based on the accumulated timing data received in the parallel form from the event summing logic. The events in the event data are specified as groups of events where each group of event is configured by one base event and at least one companion event.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: January 30, 2007
    Assignee: Advantest Corp.
    Inventors: Glen Gomes, Anthony Le
  • Charged particle beam photolithography machine, standard substrate for correcting misalignment factor of charged particle beam photolithography machine, correcting method for charged particle beam photolithography machine, and method of manufacturing electronic device
    Patent number: 7164141
    Abstract: A charged particle beam photolithography machine includes an electron gun, a deflector, a wafer stage, a standard substrate formed with a chip-shaped first mark group having a plurality of first marks and a chip-shaped second mark group having a plurality of second marks, a correction map having misalignment factors of the first marks based on positions of the second marks, and a deflection control unit for controlling an amount of deflection in the deflector. The charged particle is irradiated on a wafer while the deflection control unit makes reference to the correction map and corrects the amount of deflection as equivalent to the misalignment factors.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: January 16, 2007
    Assignee: Advantest Corp.
    Inventor: Masaki Kurokawa
  • Differential voltage measuring apparatus and semiconductor testing apparatus
    Patent number: 7138819
    Abstract: There is provided a semiconductor testing apparatus comprising a current measuring portion which converts a load current quantity at the time of application of a relatively high test voltage to a DUT to fall within a low-voltage range, and then subjects the low-voltage range to quantization conversion with a predetermined measurement resolution even when the relatively high test voltage is applied to the DUT.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: November 21, 2006
    Assignee: Advantest Corp.
    Inventor: Yoshihiro Hashimoto
  • Semiconductor test apparatus
    Patent number: 7126366
    Abstract: Good device PASS/FAIL determination is realized by measuring timings of both signals, i.e., a cross point of differential clock signals CLK and a data signal DATA output from a DUT, and obtaining a relative phase difference between both signals.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: October 24, 2006
    Assignee: Advantest Corp.
    Inventors: Masatoshi Ohashi, Toshiyuki Okayasu
  • Device for testing LSI to be measured, jitter analyzer, and phase difference detector
    Patent number: 7107166
    Abstract: LSI test equipment can acquire output data of an LSI as a device under test by a clock signal output from the LSI to be measured and acquire measurement data synchronously with the output data having jitter. The LSI test equipment includes a clock side time interpolator for acquiring the clock output from the LSI to be measured by a plurality of strobes having a predetermined timing interval and outputting it as encoded level data of time series, a data side time interpolator for acquiring the output data from the LSI to be measured by a plurality of strobes having a predetermined timing interval and outputting it as level data of time series, and a selector for receiving the level data from both of the time interpolators, selecting output data at the clock edge timing, and outputting it as data to be measured.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: September 12, 2006
    Assignee: Advantest Corp.
    Inventor: Shuusuke Kantake
  • Connection unit, a board for mounting a device under test, a probe card and a device interfacing part
    Patent number: 7098680
    Abstract: A connection unit for electrically connecting a DUT mounting board, on which an IC socket is mounted, with a testing apparatus for testing an electronic device inserted into the IC socket, the connection unit has a holding substrate provided to face the DUT mounting board and a connection-unit-side connector, which is provided on the holding substrate to be able to change a position of the connection-unit-side connector on the holding substrate, for being connected to a performance-board-side connector included in the DUT mounting board.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: August 29, 2006
    Assignee: Advantest Corp.
    Inventors: Kentaro Fukushima, Masashi Hoshino
  • MOSFET drive circuit, programmable power supply and semiconductor test apparatus
    Patent number: 7095267
    Abstract: In a programmable power supply used in a semiconductor test apparatus, high-speed switching of a large current in a current rage or an output relay is enabled. In a MOSFET drive circuit 22 of a switch portion 20 provided in a programmable power supply 10 of a semiconductor test apparatus 1, a capacitor portion 22-12 is charged with electric charges by a current from a light receiving portion 22-12 of a light insulating element 22-1. When an SWA is turned on (SWB is turned off) by changeover of the analog switch portion 22-3, a gate of each MOSFET in the MOSFET portion 21 is charged with the electric charges stored in the capacitor portion 22-12, and enters an ON state. On the other hand, when the SWB of the analog switch portion 22-3 is turned on (SWA is turned off), the gate of the MOSFET is discharged.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: August 22, 2006
    Assignee: Advantest Corp.
    Inventor: Nobuhiro Sato
  • Method for design validation of complex IC
    Patent number: 7089517
    Abstract: A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: August 8, 2006
    Assignee: Advantest Corp.
    Inventors: Hiroaki Yamoto, Rochit Rajsuman