Abstract: A repetitive bit value pattern associated to a predetermined bit position of a sequence of data words, the data words having two or more bits in a bit order, a bit position describing a position within the bit order being indicative of a value represented by the bit at the bit position, can be determined from program loop information, the program loop information having a program expression for determining an updated data word of the sequence of data words. Using the predetermined bit position, a sequence length value associated to the predetermined bit position is determined. The program expression is evaluated for a number of loop iterations indicated by the sequence length value, to obtain updated bit values associated to the predetermined bit position. The repetitive bit value pattern is determined using the updated bit values of the number of loop iterations.

Abstract: A semiconductor device includes a first wafer having i) a plurality of semiconductor dies, ii) a plurality of scribe lines adjacent one or more of the semiconductor dies, iii) a test access interface positioned in one or more of the scribe lines, wherein the test access interface has a first plurality of through-substrate conductors with a standardized physical layout, and iv) electrical couplings between at least some of the through-substrate conductors and at least one of the semiconductor dies. Methods, apparatus and systems for testing this and other types of semiconductor devices are also disclosed.

Abstract: A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.

Abstract: A system for detecting an electrostatic discharge event with respect to a device to be monitored includes a current measurement device configured to measure a current flowing via a power supply connection connecting the device to be monitored with the power supply to obtain a current measurement signal representing the current or a current component. Alternatively, a current flowing through a protective earth connection connecting the device to be monitored with the protective earth is measured to obtain the measurement signal. The system includes an electrostatic discharge event detector configured to detect an electrostatic discharge event in response to a pulse of the current measurement signal. The system may optionally include data processing of current measurement signals or values.

Abstract: A test card for testing one or more devices under test includes a plurality of test resources configured to communicate with the one or more devices under test. The test card further includes a matching circuit configured to receive a test sequence of at least two matching instructions followed by one or more processing instructions. The matching instructions define a group of resources which are to operate in accordance with the processing instructions. The matching circuit is configured to determine based on the at least two matching instructions whether a given test resource out of a plurality of test resources belongs to the group or not and to forward the processing instructions to the given test resource if the given test resource belongs to the group and to not forward the processing instructions to the given test resource if the given test resource does not belong to the group.

Abstract: Based upon a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads, a probe chip contactor is established, having a unit standard cell on the probe side of the probe chip to correspond to each of the arranged integrated circuits. The unit standard cell is stepped and repeated for the probe side of the probe chip contactor, to establish a wafer scale standard cell layout. The opposite contact side of the probe chip contactor is connectable to a central structure, e.g. a Z-block or PC board, typically comprising a fixed array of vias with fixed X, Y, and Z locations. The routing of contact side of the probe chip contactor is preferably routed automatically, such as implemented on one or more computers, to provide electrical connections between the substrate through vias and the Z-block through vias.

Abstract: A microelectronic contactor assembly can include a probe head having microelectronic contactors for contacting terminals of semiconductor devices to test the semiconductor devices. A stiffener assembly can provide mechanical support to microelectronic contactors and for connecting a probe card assembly to a prober machine. A stiffener assembly may include a main body and a plurality of mounting points, wherein at least one of the mounting points is flexibly connected to the main body by one or more laterally extending beams that has a section modulus normal to the lateral direction significantly greater than in the lateral direction. The stiffener assembly allows for differential thermal expansion of various components of the microelectronic contactor assembly while minimizing accompanying dimensional distortion that could interfere with contacting the terminals of semiconductor devices.

Abstract: An enhanced sputtered film processing system and associated method comprises one or more sputter deposition sources each having a sputtering target surface and one or more side shields extending therefrom, to increase the relative collimation of the sputter deposited material, such as about the periphery of the sputtering target surface, toward workpiece substrates. One or more substrates are provided, wherein the substrates have a front surface and an opposing back surface, and may have one or more previously applied layers, such as an adhesion or release layer. The substrates and the deposition targets are controllably moved with respect to each other. The relatively collimated portion of the material sputtered from the sputtering target surface travels beyond the side shields and is deposited on the front surface of the substrates.

Abstract: A device under test—DUT—, comprising the steps of receiving a first data sequence from the DUT in response to a first stimulus signal, wherein the data of a plurality of internal data sequences of the DUT is compressed into the first data sequence, comparing the first data sequence with expected data and for detecting errors in the first data sequence, and providing a second stimulus signal to the DUT in order to instruct the DUT to generate a second data sequence that comprises uncompressed data of the plurality of the internal data sequences at the positions where the errors have been detected.

Abstract: A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT.

Abstract: In one embodiment, an interface includes a plurality of test electronics to DUT interfaces. Each test electronics to DUT interface has at least one test electronics interface, at least one DUT interface, and an electrical coupling between the at least one test electronics interface and the at least one DUT interface. First and second subsets of the DUT interfaces are respectively positioned along the perimeters of first and second concentric shapes.

Abstract: A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.

Abstract: A device for processing test data, the device having a data input interface adapted for receiving primary test data indicative of a test carried out for testing a device under test, the primary test data being provided in a primary format, a processing unit adapted for generating secondary test data in a secondary format by transforming, by carrying out a coordinate transformation, the primary test data from the primary format into the secondary format, and a data output interface adapted for providing the secondary test data in the secondary format for storing the secondary test data in a plurality of storage units.

Abstract: A tester for testing a device under test has a first channel unit and a second channel unit. The first channel unit has a corresponding first pin connection for a signal from a device under test, a corresponding first test processor adapted to process, at least partially, data obtained from the first pin connection, and a corresponding first memory coupled with the first test processor and adapted to store data provided by the first test processor. The first channel unit is adapted to transfer at least a part of the data obtained from the first pin connection to the second channel unit as transfer data. The second channel unit has a corresponding second test processor adapted to process, at least partly, the transfer data from the first channel unit.

Abstract: In one embodiment, a method of operating a number of data formatters 1) blocks execution of a tester's test processes that generate test results, the test results pertaining to test of at least one device under test (DUT); 2) launches a number of data formatters, operable to format the test results, while execution of the test processes is blocked; and 3) upon determining that the number of data formatters has successfully launched, removing the block. Other embodiments are also disclosed.

Abstract: A test module for a test apparatus for testing a device under test, the test module being adapted for performing a specific test function and having a universal section adapted to provide test resources being unspecific with regard to the test function of the test module, the universal section having a control interface adapted to be connected to a central control device of the test apparatus, and having a specific section to be coupled to the universal section and adapted to provide test resources being specific with regard to the test function of the test module, the specific section having a device under test interface adapted to be connected to the device under test.

Abstract: In accordance with one embodiment of the invention, a system is provided that comprises a first terminal for receiving an input testing signal during operation; a plurality of input/output terminals coupled with the first terminal; wherein the input/output terminals are configured to parallel output respective output testing signals during parallel output operation; wherein the input/output terminals are configured to parallel input testing response signals during parallel input operation from devices under test; and wherein each of the input/output terminals is electrically isolated during operation from the remaining plurality of input/output terminals.

Abstract: The present invention relates to a method for evaluating an output signal of a Device Under Test, wherein said Device Under Test outputs said output signal in response to an input signal provided by an Automated Test Equipment, said method including the steps of: generating a difference signal representing the difference between said output signal of said Device Under Test and a reference signal, integrating said difference signal during a clock period respectively, resulting in an integrated difference signal, and evaluating said integrated difference signal with regard to a bit level to be assigned to said output signal of said Device Under Test during the respective clock period.

Abstract: In one embodiment, a test system has a set of test electronics for testing a device under test (DUT). The test system also has at least one test electronics to DUT interface having a zero insertion force (ZIF) connector. Each ZIF connector has a ZIF connector to DUT clamping mechanism configured to i) apply a first orthogonal force to a probe card that interfaces with a DUT, by pressing the ZIF connector against the probe card, and simultaneously ii) exert at least one second orthogonal force on the probe card, the at least one second orthogonal force being opposite in direction to the first orthogonal force.

Abstract: A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.