Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.

Abstract: A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The decoder buffer level limits are specified in terms of a maximum number of encoded frames (or duration). The transmitter can predict the number of encoded frames, Fpred, in the decoder buffer and transmit the value, Fpred, to the receiver with the audio data. If the transmitter determines that the decoder buffer level is becoming too high, the frames being generated by the encoder are too small and additional bits are allocated to each frame for each of the N programs. Likewise, if the transmitter determines that the decoder buffer level is becoming too low, the frames being generated by the encoder are too big and fewer bits are allocated to each frame for each of the N programs. The transmitted predicted buffer level, Fpred, can also be employed to (i) determine when the decoder should commence decoding frames; and (ii) synchronize the transmitter and the receiver.

Abstract: Techniques are provided for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. A reduced state sequence estimation (RSSE) decoder is provided for a multidimensional code. A multidimensional code symbol comprises a number of symbol components of lower dimensionality. The RSSE decodes comprises at least one branch metric unit that calculates branch metrics for a received signal based on intersymbol interference and intrasymbol interference estimates, the at least one branch metric unit compensating for intrasymbol interference caused by symbol components within a current multidimensional code symbol; and a decision feedback unit that processes survivor symbols to calculate the intersymbol interference estimates for different code states of the multidimensional code and channels used to transmit the multidimensional code.

Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ?? rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

Abstract: A video delivery system and service for use with a video presentation and methods of delivering and receiving a video representation. In one embodiment, a method of receiving a video representation includes receiving a request to program a video viewing device to record a video presentation employing a selected content. The method also includes remotely programming the video viewing device employing the selected content to provide the video representation.

Abstract: Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoder is provided for encoding message symbols, m0 through mN-1, to generate a codeword that includes the message symbols, m0 through mN-1, and one or more check symbols. The error correction encoder comprises a linear feedback shift register having one or more flip-flops to generate the check symbols after shifting the message symbols, m0 through mN-1, through the linear feedback shift register. An error correction decoder is also provided for decoding a codeword that includes message symbols, m0 through mN-1, and one or more check symbols. The error correction decoder comprises a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting the message symbols, m0 through mN-1, and the one or more check symbols through the linear feedback shift register.

Abstract: In a system including a processor and memory coupled to the processor, a method of device failure analysis includes the steps of: upon each error detected within a test series performed on a device, the processor storing within a table in the memory an address at which the error occurred in the device and storing a bit position of each failed bit corresponding to that address; for each unique address at which at least one error occurred, determining how many different bit positions corresponding to the address failed during the test series; and based on results of the test series, determining whether the device failed the test series.

Abstract: Techniques are disclosed for automatic generation of a location-indicative instruction displayable to one or more users in a communication system which includes a wireless network comprising a plurality of user devices adapted for communication with at least one access point device. A test of a communication link between at least one of the user devices and the access point device is initiated. Based at least in part on a result of the test, an instruction displayable to a user associated with a given one of the user devices is generated, the instruction being indicative of a location at which the given user device is expected to obtain a particular level of data throughput performance.

Abstract: In accordance with the principles of the present invention utilizing the BLUETOOTH specification Cordless Telephony profile, incoming calls to a cell phone including a Gateway role can be routed to another piconet device (e.g., another cell phone including a Terminal role. Two cell phones with BLUETOOTH capability each include the Cordless Telephony Profile. The cell phone receiving the call acts as a PSTN cordless telephone Gateway cell phone via the cellular network, while the other cell phone acts as a cordless telephone Terminal cell phone. The cordless telephone Terminal cell phone then acts as an extension to the Gateway cell phone allowing both calls to the Gateway cell phone to be answered at the Terminal cell phone, and even allowing calls by the Gateway cell phone to be originated by the Terminal cell phone.

Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Abstract: A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The transmitter predicts the number of encoded frames, Fpred, in the buffer having a limited level and transmits the value, Fpred, to the receiver with the frame. If the transmitter determines that the decoder buffer level is high, the frames being generated by the encoder are small and additional bits are allocated to each frame for each of the N programs. Likewise, if the transmitter determines that the decoder buffer level is becoming low, the frames being generated by the encoder are big and fewer bits are allocated to each frame for each of the N programs. The transmitted predicted buffer level, Fpred, can also be employed to (i) determine when the decoder should commence decoding frames; and (ii) synchronize the transmitter and the receiver clock using feedback depending on the compared level of the decoder to the actual level to Fpred.

Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Abstract: Methods and apparatus are provided for counter-based digital frequency lock detection. A counter-based digital frequency lock detector in accordance with the present invention comprises a reference counter clocked by a reference clock and a target counter clocked by a target clock. The target counter is n bits and n is less than a number of bits of the reference counter. A frequency offset violation of the target clock is detected by comparing a value of the target counter to an n bit counter.

Abstract: An integrated circuit device for use in a line card of a network node of a digital networking system is provided. The integrated circuit device is capable of intercepting one or more control messages from at least one CPE device. The one or more control messages correspond to at least an operational status of at least one TE device associated with the at least one CPE device. The integrated circuit device is also capable of transmitting one or more rate control messages to a network processor of the network node to adapt bandwidth utilization and provide adapted data traffic flow to at least one CPE device in relation to the operational status of the at least one TE device.

Abstract: Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.

Abstract: An audio device includes a Bluetooth receiver, a Bluetooth transmitter, a speaker and a housing. The Bluetooth receiver is capable of wirelessly receiving signals in at least two audio channels. The Bluetooth transmitter is capable of wirelessly retransmitting at least a first one of the two audio channels. The speaker plays the second one of the two audio channels. The housing contains the Bluetooth receiver, the Bluetooth transmitter, and the ear phone. The housing is shaped to fit in or on an ear of a user.

Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.

Abstract: A processor configured to operate with multiple operation codes for each of a plurality of instructions comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is configured to decode a first operation code to produce a given one of the instructions and to decode a second operation code different than the first operation code to also produce the given instruction. Thus, the same instruction is produced for execution by the processing circuitry regardless of whether the first operation code or the second operation code is decoded. The assignment of multiple operation codes to a given instruction may occur in conjunction with the design of the processor, and dynamic selection of a particular one of those operation codes may be performed in conjunction with assembly of code for execution by the processor.