Abstract: Described embodiments provide rate setting for nodes of a scheduling hierarchy of a network processor. The scheduling hierarchy is a tree structure having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager queues received tasks in a queue of the scheduling hierarchy associated with a data flow of the task. The queue has a parent scheduler at each level of the hierarchy up to the root scheduler. A scheduler selects a child node for transmission based on a number of arbitration credits in an arbitration credit bucket of each child. An arbitration credit value is determined for each child by maintaining a time stamp value corresponding to a time value of a previous selection of the child node and determining an elapsed time value based on the time stamp value and a current time value, scaled by a scaling factor.

Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract: An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology.

Abstract: The present invention provides method of manufacture for a printed wiring board. The printed wiring board constructed according to the teachings of the present invention includes a printed wiring board dielectric layer having conductive foils located on at least two sides thereof. The printed wiring board further includes a solid core conductive material interconnecting the conductive foils.

Abstract: In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated.

Abstract: A network processor or other type of processor includes translation configuration circuitry which allows programmable configuration of logical-to-physical address translation on a per-client basis for multiple clients of the processor. In one aspect of the invention, the processor stores translation configuration information for a client. A read or write request from the client includes a logical address. The logical address is processed utilizing the stored translation configuration information for the client to generate a physical address. The physical address is utilized to access an internal or external memory.

Abstract: In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined.

Abstract: A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.

Abstract: A communications circuit includes a filter module with a sampling window, a control module, and an input buffer. The control module has a ray parameter interface to obtain information regarding significant ray changes that make it desirable to re-position the sampling window. The control module determines re-positioning parameters, responsive to this information, which reflect the re-positioning of the sampling window. The input buffer obtains samples of a received signal and outputs received signal data to the filter module. The filter module obtains the re-positioning parameters from the control module, and the filter module and control module temporally re-position the sampling window in duration and/or location in accordance with the re-positioning parameters, and output a filtered chip.

Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Abstract: In one embodiment, a receiver for a frame of media packets employing the real-time transmission protocol (RTP) and forward error correction (FEC) is disclosed. The receiver comprises a packet buffer and an FEC decoder. After a packet is received by the packet buffer, the FEC decoder reads the packet and, as part of FEC processing, performs an XOR operation on the packet, without waiting for the entire frame (or, indeed, for any subsequent packet of the frame) to be received. The XOR operation results are accumulated until sufficient packets are received to reconstruct a missing packet in the frame. Because the XOR operations are performed immediately after a packet is received, without any delay from waiting for subsequent packets, the receiver has a very low latency, and the packet buffer may be relatively small.

Abstract: A carrier signal acquisition technique is disclosed. An improved course carrier frequency offset algorithm is employed in conjunction with a conventional fine carrier frequency offset algorithm. The course carrier frequency offset algorithm estimates large offsets that are multiples of the carrier spacing that may occur at system startup. A spectral null is placed in the center of the transmit spectrum and is thereafter located in a received signal. The position of the spectral null provides an estimate of the local oscillator carrier offset. A frequency finite state machine (FSM) processes a number of metrics to ensure the reliability of the course carrier frequency offset and of transitions between acquisition and tracking modes. The frequency FSM will utilize the frequency offset (modin) generated by a MODSC algorithm provided one or more predefined thresholds are satisfied.

Abstract: A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).

Abstract: One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage.

Abstract: In one embodiment, a low cost, simple circuit for detecting an off-hook condition of a telecommunication line comprising tip and ring signal lines is provided. The circuit comprises a voltage divider for coupling between the tip and ring lines without an intervening transistor and having a node at which is presented a scaled version of a voltage across the voltage divider. The circuit further comprises a transistor having a control terminal coupled to the node, a first current flow terminal coupled to a voltage source, and a second current flow terminal coupled to an output terminal, wherein the output terminal bears a value that is indicative of a voltage across the tip and ring lines and thus whether the telecommunication line is off-hook.

Abstract: A way for securely protecting secret information—for example, a secret key—in a programmed electronic device is provided. A technique is disclosed for protecting secret information in a programmed electronic device that includes a non-trusted memory containing software, a data memory containing the secret information, and an access restriction logic unit that is adapted to allow or block access to the secret information wherein the secret information is adapted to be used for verifying the integrity of the software. In one embodiment, when starting up the programmed electronic device, the access restriction logic unit allows access to the secret information. Then the secret information is accessed for use in verifying the integrity of the software, and subsequently the access restriction logic unit blocks further access to the secret information. Embodiments of a semiconductor device and a programmed electronic device comprising similar features are also disclosed.

Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract: Methods and apparatus are provided for joint adaptation of filter values in two communicating devices, such as a link partner and a link device. The disclosed joint adaptation process initially adapts the filter coefficient values in a first of the two communicating devices until a predefined stopping criteria is satisfied. Thereafter, the filter coefficient values in a second of the two communicating devices are adapted once the predefined stopping criteria for the first communicating device is satisfied. The filter coefficient values can comprise coefficient values of a multi-tap filter. The predefined stopping criteria may determine, for example, whether the first of the two communicating devices is overequalized. The filter coefficient values can be determined by including a contribution of only certain cursor tap values of the channel impulse response.

Abstract: A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.