Patents Assigned to Akita Electronics Co., Ltd.
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Patent number: 7262480Abstract: A high frequency power amplifying device has two amplifying lines. Each amplifying line has a configuration in which a plurality of amplifying stages are connected in cascade having two source voltage terminals, of which one is connected to the first amplifying stage of one amplifying line and to the remaining amplifying stages of the other amplifying line, and the other, to the first amplifying stage of the latter amplifying line and to the remaining amplifying stages of the former amplifying line. An air core coil with a low D.C. resistance, formed by spirally winding a copper wire of about 0.1 mm in diameter, is connected in series between the final amplifying stage of each amplifying line and the source voltage terminal.Type: GrantFiled: March 21, 2001Date of Patent: August 28, 2007Assignees: Hitachi, Ltd., Eastern Japan Semiconductor Technologies, Akita Electronics Co., Ltd.Inventors: Toshihiko Kyogoku, Tadashi Kodu, Kiyoharu Mochiduki, Sakae Kikuchi, Akio Ishidu, Yoshihiko Kobayashi, Masashi Maruyama, Iwamichi Kojiro, Susumu Sato
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Patent number: 6912172Abstract: Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management.Type: GrantFiled: November 24, 2003Date of Patent: June 28, 2005Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Kazuki Honma, Yoshiki Kawajiri, Masashi Wada, Mikio Sugawara, Hirofumi Sonoyama
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Publication number: 20040113176Abstract: Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management.Type: ApplicationFiled: November 24, 2003Publication date: June 17, 2004Applicants: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Kazuki Honma, Yoshiki Kawajiri, Masashi Wada, Mikio Sugawara, Hirofumi Sonoyama
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Patent number: 6693346Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: January 14, 2003Date of Patent: February 17, 2004Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 6686663Abstract: Two memory chips mounted over a base substrate have the same external size and a flash memory of the same memory capacity formed thereon. These memory chips are mounted over the base substrate with one of them being overlapped with the upper portion of the other one, and they are stacked with their faces being turned in the same direction. The bonding pads BP of one of the memory chips are disposed in the vicinity of the bonding pads BP of the other memory chip. In addition, the upper memory chip is stacked over the lower memory chip in such a way that the upper memory chip is slid in a direction (X direction) parallel to the one side of the lower memory chip and in a direction (Y direction) perpendicular thereto in order to prevent partial overlapping of it with the bonding pads BP of the lower memory chip.Type: GrantFiled: July 15, 2002Date of Patent: February 3, 2004Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Masachika Masuda, Toshihiko Usami
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Patent number: 6670220Abstract: A non-leaded semiconductor device which does not cause a flaw and contamination with a foreign substance on mounting surfaces of external electrode terminals of another non-leaded semiconductor device, and a method of fabricating the same. In fabrication of the non-leaded semiconductor device, a matrix-type leadframe containing a matrix of a plurality of unit leadframe patterns is prepared, a semiconductor chip is secured on each unit leadframe pattern, conductive wires are connected between electrodes of the semiconductor chip and inner ends of terminal leads of each unit leadframe pattern, and then single-sided molding is performed to encapsulate the semiconductor chip, conductive wires, and inner end parts of terminal leads in a package part. In this single-sided molding, a contact-preventive part thicker than the package part is formed outside the package part using injected resin.Type: GrantFiled: August 28, 2001Date of Patent: December 30, 2003Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Tadaki Sakuraba, Youkou Ito, Hidehiro Takeshima, Yoshiaki Tamai, Toru Saga
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Patent number: 6667928Abstract: Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management.Type: GrantFiled: April 26, 2002Date of Patent: December 23, 2003Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Kazuki Honma, Yoshiki Kawajiri, Masashi Wada, Mikio Sugawara, Hirofumi Sonoyama
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Patent number: 6654481Abstract: A mobile object combination detection apparatus includes a plurality of moving image input units, a plurality of mobile object detection units each connected to one of the moving image input units, and a combination determination unit. Each of the plurality of mobile object detection unit detects a mobile object at a predetermined position on a moving image inputted thereto from the moving image input unit, and sends detection information to the combination determination unit. The combination determination unit compares the detection information of the mobile object sent thereto from each of the mobile object detection unit with a predetermined condition to determine that a target mobile object is detected when the detection information satisfies the predetermined condition.Type: GrantFiled: April 11, 2001Date of Patent: November 25, 2003Assignees: Hitachi, Ltd., Akita Electronics, Co., Ltd.Inventors: Hirokazu Amemiya, Toshihide Saga, Shinji Hashimoto, Yasuyuki Ooki
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Patent number: 6649931Abstract: A semiconductor device includes a first semiconductor chip having a non-volatile memory array which has a first memory area for storing input information of usual operation, and a second memory area for storing historical information of an electrical characteristic test of the first memory area. The device further includes a second semiconductor chip having a volatile memory array with a third memory area for storing input information of usual operation. Historical information of an electrical characteristic test of the third memory area of the second semiconductor chip is stored into the second memory area of the first semiconductor chip.Type: GrantFiled: November 13, 2001Date of Patent: November 18, 2003Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Kazuki Honma, Terutaka Okada, Fumiaki Kitajima, Takahiro Hatazawa, Hiroyuki Motomatsu, Katsuhiro Haruyama
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Patent number: 6639323Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.Type: GrantFiled: October 23, 2001Date of Patent: October 28, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Akita ELectronics Co., Ltd.Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino
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Patent number: 6618298Abstract: The semiconductor memory device of the present invention is provided with a switching element comprised of a single channel MOS transistor at a halfway of a path used to transmit a high voltage supplied to the memory array via the external terminal at the time of a test performance, so that the switching element is turned off when a word line is changed to another, thereby resetting of the supply voltage having been required conventionally for each test performance is omitted.Type: GrantFiled: May 14, 2002Date of Patent: September 9, 2003Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Kazuki Honma, Masashi Wada, Shuichi Kuwahara
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Patent number: 6617196Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.Type: GrantFiled: December 21, 2001Date of Patent: September 9, 2003Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Akihiko Iwaya, Toshio Sugano, Susumu Hatano, Yutaka Kagaya, Masachika Masuda
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Patent number: 6584211Abstract: A mobile object combination detection apparatus includes a plurality of moving image input units, a plurality of mobile object detection units each connected to one of the moving image input units, and a combination determination unit. Each of the plurality of mobile object detection unit detects a mobile object at a predetermined position on a moving image inputted thereto from the moving image input unit, and sends detection information to the combination determination unit. The combination determination unit compares the detection information of the mobile object sent thereto from each of the mobile object detection unit with a predetermined condition to determine that a target mobile object is detected-when the detection information satisfies the predetermined condition.Type: GrantFiled: October 30, 1998Date of Patent: June 24, 2003Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Hirokazu Amemiya, Toshihide Saga, Shinji Hashimoto, Yasuyuki Ooki
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Patent number: 6538331Abstract: Two memory chips mounted over a base substrate have the same external size and a flash memory of the same memory capacity formed thereon. These memory chips are mounted over the base substrate with one of them being overlapped with the upper portion of the other one, and they are stacked with their faces being turned in the same direction. The bonding pads BP of one of the memory chips are disposed in the vicinity of the bonding pads BP of the other memory chip. In addition, the upper memory chip is stacked over the lower memory chip in such a way that the upper memory chip is slid in a direction (X direction) parallel to the one side of the lower memory chip and in a direction (Y direction) perpendicular thereto in order to prevent partial overlapping of it with the bonding pads BP of the lower memory chip.Type: GrantFiled: January 26, 2001Date of Patent: March 25, 2003Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Masachika Masuda, Toshihiko Usami
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Patent number: 6521993Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: April 18, 2002Date of Patent: February 18, 2003Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor Ltd., Akita Electronics Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 6515371Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.Type: GrantFiled: October 23, 2001Date of Patent: February 4, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Akita Electronics Co., Ltd.Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino
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Patent number: 6452266Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.Type: GrantFiled: December 21, 2001Date of Patent: September 17, 2002Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Akihiko Iwaya, Toshio Sugano, Susumu Hatano, Yutaka Kagaya, Masachika Masuda
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Patent number: 6424030Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: May 24, 2001Date of Patent: July 23, 2002Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
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Patent number: 6388318Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.Type: GrantFiled: May 3, 2000Date of Patent: May 14, 2002Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.Inventors: Akihiko Iwaya, Toshio Sugano, Susumu Hatano, Yutaka Kagaya, Masachika Masuda
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Patent number: 6307269Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.Type: GrantFiled: July 10, 1998Date of Patent: October 23, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Akita Electronics Co., Ltd.Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino